PG2

PowerPC System Design

This course has been designed for developers involved in a PowerPC development who want to understand generic mechanisms

Objectives

  • This course explains the objectives of mechanisms used to boost the performance and the way they are implemented in various PowerPCs : cache / cache coherency, pipeline, MMU, exceptions.
  • This gives to the attendees a wider overview of the state of the art in these domains.
  • The course details the instructions required to write program in supervisor mode to adapt the behaviour of the core to specific needs.
  • Task switch requirements are highlighted.
  • Debug facilities implemented in PowerPCs (hardware breakpoints, real-time trace, watchpoints) are studied through the use of Lauterbach TRACE32 debugger.
A lot of programming examples have been developed by ACSYS to explain the PowerPC assembly language.
•  They have been developed with GNU compiler and are executed under Lauterbach debugger.
A more detailed course description is available on request at training@ac6-training.com
  • Basic knowledge of processor or DSP.
  • Theoretical course
    • PDF material in English (printed for face-to-face); online over Teams.
    • Trainer assistance throughout.
  • Each session starts with a trainee check-in.
  • Any embedded systems engineer or technician with the above prerequisites.
  • Prerequisites are checked before the course starts, against the prerequisites published on this page.
  • Throughout the course, learning is assessed continuously: end-of-section quizzes and direct observation by the trainer.
  • At the end of the course, each participant receives a training completion certificate.

Course Outline

  • PowerPC programming environment : 32-bit PowerPC architecture, Book E, 64-bit architecture
  • Register set, GPR vs SPR, HID registers
  • Data type instantiation for PowerPC
  • Pointers management (Addressing modes)
  • User and supervisor functions call and return (EABI, C-to-assembly interface)
  • Sections, benefits of small data sections
  • Locating code and data in memory , linker command file
  • Reset, what is to be done before calling the main() : Cstart program
  • Superscalar operation
  • Mechanisms used to boost performance : branch prediction, branch target address cache, link stack
  • Guidelines to optimize execution time
  • Serializations, isync instruction, determining when this instruction is really required
  • Highlighting the frequency domains present in PowerPC : core and bus interface
  • Decoupling the core from cache and bus through load and store buffers
  • Default ordering of load and store transactions
  • Enforcing the ordering through eieio (called mbar in Book E) and sync (called msync in Book E) instructions
  • Purpose of the Guarded attribute
  • Consequence for high level development of IO drivers
  • Requirements for kernels enabling dynamic memory mapping
  • Single process multi-thread versus multiprocess multi-thread kernels
  • Objectives of the MMU : page protection, definition of page attribute, address translation
  • Segment and page translation
  • Table search mechanisms : benefits of a software table search
  • Operation of TLB caches
  • TLB programming, static initialization
  • Introduction to cache memory
  • Cache organization
  • Write policies
  • Replacement algorithms
  • Data flow between external main memory
  • Distinguishing private memory that is accessed only by the core and shared memory that can be accessed by the core and other masters (DMA or CPU)
  • Software enforced coherency
  • Hardware enforced coherency
  • Software exceptions vs interrupts
  • Save / restore registers
  • Organization of an exception handler : prolog, body and epilog
  • How to find the cause of the exception, syndrome registers
  • Design of a generic exception handler based on a vector table
  • Interrupt management, addition of a critical interrupt in Book E
  • Integrated interrupt controller
  • Requirements for interrupt nesting
  • Management of boolean semaphores, lwarx / stwcx. instruction pair
  • Stack switch, use of SPRG registers
  • Definition of the set of registers that determine the stack state
  • Management of task lists in single and multi processor systems
  • On-chip debug logic
  • Restrictions of JTAG debug
  • Hardware breakpoints
  • Real-time trace
  • Debugging software when caches are active
  • The performance monitor
Duration
4 days
Inquiry

This course can be scheduled upon request. Click the 'Inquire' button to contact us.

Pricing

Courses are quoted individually, with no list price. The price depends on the duration, the number of participants, the delivery mode and the technical resources provided.

For more information on our pricing, see more.

More

To book a training session or for more information, please contact us on info@ac6-training.com.

Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.

You can also fill and send us the registration form

This course can be provided either remotely, in our Paris training center or worldwide on your premises.

Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 1 week before the course start.

Last update of course schedule: 27 June 2026

Booking one of our trainings is subject to our General Terms of Sales

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