MPC824X implementation Training | Ac6 Training

ac6-training, un département d'Ac6 SAS
EN
✓EnglishFrench
 
go-up

ac6 › ac6-training › Processors › NXP › MPC824X implementation
Inquire
FPQ2MPC824X implementation
This course PowerQUICC II devices, such as MPC8247
Objectives
  • The course describes various implementation of the MPC824X: PCI host and PCI IO device.
  • The course details the address translation mechanism used to access from core to PCI and from PCI to SDRAM.
  • The course focuses on low level programming and EABI understanding.
  • The hardware implementation is studied, particularly the SDRAM controller.
  • The course explains the scatter / gather operation of the DMA channel.
  • Synchronization between masters through message is highlighted.
A lot of programming examples have been developed by ACSYS to explain the boot sequence and the operation of complex peripherals, such as PCI bridge and SDRAM controlle.
•  They have been developed with Diab Data compiler and are executed under Lauterbach debugger.
A more detailed course description is available on request at training@ac6-training.com
  • Experience of a 32-bit processor or DSP is mandatory.
  • Knowledge of PCI is mandatory, see our course reference IC1 - PCI 3.0 course
  • Theoretical course
    • PDF course material (in English) supplemented by a printed version for face-to-face courses.
    • Online courses are dispensed using the Teams video-conferencing system.
    • The trainer answers trainees' questions during the training and provide technical and pedagogical assistance.
  • At the start of each session the trainer will interact with the trainees to ensure the course fits their expectations and correct if needed
  • Any embedded systems engineer or technician with the above prerequisites.
  • The prerequisites indicated above are assessed before the training by the technical supervision of the traineein his company, or by the trainee himself in the exceptional case of an individual trainee.
  • Trainee progress is assessed by quizzes offered at the end of various sections to verify that the trainees have assimilated the points presented
  • At the end of the training, each trainee receives a certificate attesting that they have successfully completed the course.
    • In the event of a problem, discovered during the course, due to a lack of prerequisites by the trainee a different or additional training is offered to them, generally to reinforce their prerequisites,in agreement with their company manager if applicable.

Course Outline

  • Internal data paths, CCU operation
  • Benefits of the snooper, sharing of cache enabled regions
  • Mapping detail
  • Address translation from core to PCI Memory space
  • Address translation from PCI to SDRAM
  • Selection of the base address of internal memory mapped status and control registers
  • Self configuration of the MPC824X through input sampling
  • Requirements of the boot routine
  • 603e pipeline introduction
  • instruction queue, superscalar execution, register renaming, out-of-order execution
  • Dispatch conditions, completion conditions
  • FPU and LSU internal pipeline operation
  • Execution serialization
  • Branch management : static prediction
  • Guarded memory
  • Cache basics
  • Cache related page / block attributes
  • 603e L1 cache : LRU algorithm, HID0 programming interface
  • Software L1 data cache flush
  • Cache coherency : the MEI 3-bit L1 data line state
  • MEI snooping sequences involving the 603e core and a PCI master
  • Branch instructions
  • Integer load / store instructions, boolean semaphore management
  • Integer arithmetic and logic instructions
  • IEEE754 basics
  • FPU operation
  • The EABI
  • Code and data sections, small data areas benefits
  • Cache related instructions
  • PowerPC timers : TB and DEC
  • MMU goals
  • The PowerPC address processing : real mode, bloc address translation, segment / page mode
  • WIMG attributes definition
  • Process protection through VSID selection
  • TLB organization
  • Page translation
  • MMU implementation in real-time sensitive applications
  • Exception state saving and restoring
  • Exception management
  • Recoverable vs non recoverable interrupts
  • Requirements to support exception nesting
  • Tagging of the master accessing SDRAM
  • Hardware vs software breakpoint
  • JTAG emulation
  • Real time trace requirements
  • Pinout
  • Clocking, selection of the PLL ratio
  • DLL benefit, electrical interface
  • SDRAM basics, page mode, refresh, timing diagrams
  • SDRAM related registers initialisation according to IBM SDRAM device features
  • The Flash EPROM controller
  • Port-X
  • Commands supported when the bridge is a PCI master and when the bridge is a PCI target
  • Access to the local SDRAM address space by a PCI master
  • Generation of configuration transactions
  • The interrupt controller
  • Internal timers
  • Synchronization mechanisms : doorbell registers, I2O compliant messaging
  • The DMA controller, selection of the command generated on the PCI side
  • The I2C controller
Duration
5 days
Inquiry

This course can be scheduled upon request. Click the 'Inquire' button to contact us.

More

To book a training session or for more information, please contact us on info@ac6-training.com.

Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.

You can also fill and send us the registration form

This course can be provided either remotely, in our Paris training center or worldwide on your premises.

Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 1 week before the course start.

Last update of course schedule: 25 April 2026

Booking one of our trainings is subject to our General Terms of Sales

Related Courses