i.MX28 + LTIB Training | Ac6 Training

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FA0i.MX28 + LTIB
This course describes the i.MX28 processor family and Linux Target Image Builder tool
Objectives
  • This course has 4 main objectives:
    • Describing the hardware implementation and highlighting the pitfalls
    • Describing the ARM926EJ-S core architecture
    • Describing the units which are interconnected to other modules, such as clocking, interrupt controller and DMA controller, because the boot program generally has to modify the setting of these units
    • Describing independent I/O modules and their drivers.
  • Note that this course has been designed from the architecture of the most complex iMX28, the i.MX287
    • Consequently, a chapter has been designed by Acsys for each possible integrated IP
    • According to the actual reference chosen by the customer, some chapters may be removed.

  • Products and services offered by ACSYS:
    • ACSYS is able to assist the customer by providing consultancies. Typical expertises are done during board bringup, hardware schematics review, software debugging, performance tuning.
    • ACSYS has also an expertise in Linux porting.

ACSYS has developed a tutorial to explain how to use LTIB to generate both Linux kernel and Root File System.
A more detailed course description is available on request at training@ac6-training.com
This document is necessary to tailor the course to specific customer needs and to define the exact schedule.

  • Theoretical course
    • PDF course material (in English) supplemented by a printed version for face-to-face courses.
    • Online courses are dispensed using the Teams video-conferencing system.
    • The trainer answers trainees' questions during the training and provide technical and pedagogical assistance.
  • At the start of each session the trainer will interact with the trainees to ensure the course fits their expectations and correct if needed
  • Any embedded systems engineer or technician with the above prerequisites.
  • The prerequisites indicated above are assessed before the training by the technical supervision of the traineein his company, or by the trainee himself in the exceptional case of an individual trainee.
  • Trainee progress is assessed by quizzes offered at the end of various sections to verify that the trainees have assimilated the points presented
  • At the end of the training, each trainee receives a certificate attesting that they have successfully completed the course.
    • In the event of a problem, discovered during the course, due to a lack of prerequisites by the trainee a different or additional training is offered to them, generally to reinforce their prerequisites,in agreement with their company manager if applicable.

Course Outline

  • ARM core based architecture
  • Interconnect, indicating the features of AXI, AHB and APB
  • Clarifying the internal data and instruction paths
  • Integrated memories
  • SoC mapping
  • CPU block diagram
  • V5TE software architecture
  • Memory Management Unit
  • Instruction and data caches
  • Debug facilities
  • 128-bit vectored interrupt collector to generate core IRQ
  • Non-vectored interrupt collection mechanism to generate core FIQ
  • Implementing interrupt nesting
  • Generating the vector address
  • Power Management Unit
  • Reset
  • Clock generation subsystem
  • Explaining the global AHB / AXI / APB interconnect organization
  • 3-layer AHB parameterizing
  • PL301 AXI crossbar parameterizing
  • Dual APB
  • DMA
  • Power pins
  • Pinout
  • GPIO module
  • Internal SRAM
  • Integrated Mask-Programmable On-Chip ROM
  • On-Chip One-Time-Programmable (OCOTP) ROM
  • External Memory Interface
  • DDR-2 controller
  • General Purpose Media Interface
  • Timers and rotary decoder
  • Pulse Width Modulator channels
  • Real-Time Clock
  • Low-Resolution ADC (LRADC) and Touch-Screen interface
  • Single Channel High Speed ADC (HSADC)
  • Security Features
  • Data Co-Processor (DCP)
  • Customer-Programmable One-Time-Programmable (OTP) ROM
  • 20-Bit Correcting ECC Accelerator (BCH)
  • Synchronous Serial Ports
  • UART
  • I2C
  • USB
  • Fast Ethernet with IEEE1588
  • 3-port L2 switch
  • Dual Serial Audio Interface (SAIF), Three Stereo Pairs
  • SPDIF transmitter
  • Highly Flexible Display Controller (LCDIF)
  • Pixel Processing Pipeline (PXP)
  • Introducing the tools required to generate the kernel image
  • What is required on the host before installing LTIB
  • Common package selection screen
  • Common target system configuration screen
  • Building a complete BSP with the default configurations
  • Creating a Root Filesystem image
  • Re-configuring the kernel under LTIB
  • Selecting user-space packages
  • Setup the bootloader arguments to use the exported RFS
  • Debugging Uboot and the kernel by using Trace32
  • Command line options
  • Adding a new package
  • Other deployment methods
  • Creating a new package and integrating it into LTIB
    • A lot of labs have been created to explain the usage of LTIB
Duration
5 days
Inquiry

This course can be scheduled upon request. Click the 'Inquire' button to contact us.

More

To book a training session or for more information, please contact us on info@ac6-training.com.

Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.

You can also fill and send us the registration form

This course can be provided either remotely, in our Paris training center or worldwide on your premises.

Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 1 week before the course start.

Last update of course schedule: 25 April 2026

Booking one of our trainings is subject to our General Terms of Sales

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