+ +
- -
Systèmes d'Exploitation
Calendrier  Détails
Programmation
 
Calendrier  Détails
Processeurs ARM
 
Calendrier  Détails
Processeurs PowerPC
 
 
 
 
Calendrier  Détails
Communications
 
 
Calendrier  Détails
+ +
> >
- -

 
ac6 >> ac6-training >> Programmation >> Logique Programmable >> Xilinx - Designing with Ethernet MAC logicores Télécharger le catalogue Télécharger la page Ecrivez nous Version imprimable

HX3 Xilinx - Designing with Ethernet MAC logicores

This course covers the implementation of the Ethernet MAC Xilinx logicores.

formateur
Objectives
  • Utilize various Ethernet cores, used either in standalone mode or as a peripheral in a processor-based design.
  • Determine the appropriate core to use.
  • Develop software to drive the core and achieve desired functionality.
  • Integrate hard and soft IP into the EDK.

  • This course is delivered by Ac6 engineers, expert of Gigabit Ethernet, who has developed trainings on 802.3 / 802.1 specification and Gigabit Ethernet implementation in AMCC, Intel, NXP processors and Marvell switches.
Xilinx software (ISE) is used to synthesize and implement practical examples, Mentor Graphics ModelSim is used for simulation.
A more detailed course description is available on request at training@ac6-training.com
Prerequisites
  • Knowledge of Ethernet is recommended, see our course reference N1.
  • Experience with Xilinx ISE and EDK software tools is recommended.

DAY 1
  • Ethernet basics
  • Network protocols
    • Lab1 : Analyzing Ethernet frames
  • Physical layer
  • Local Link interface
    • Lab2 : VLAN and Jumbo frames
  • Xilinx EMAC solutions
DAY 2
    • Lab3 : Implementation
  • EMAC and EMAC lite
    • Lab4 : EMAC peripheral in loopback mode
  • GEMAC
  • TEMAC
    • Lab5 : TEMAC in loopback mode
  • 10GE MAC
    • Lab6 : Analyzing 10GE MAC frames