Programmable components fundamentals Training | Ac6 Training

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V0Programmable components fundamentals
This training is intended to professional who want to use or maintain programmable components
Objectives
  • Knowing the programmable logic basics
  • Knowing the general offer for CPLDs and FPGAs
  • Understand application description in HDL
  • Understand the logical synthesis notions and process flow
  • Discover FPGA programming in VHDL and Verilog
  • Understand how to elaborate and simulate a design
  • A PC in pairs
  • Xilinx ISE Design Suite 14.4 Webpack Edition
  • A Nexys-3 (Xilinx Spartan6-based) board
  • Knowledge of digital technology
  • Concepts of Boolean algebra
  • Some programming concepts are desirable (whatever language)
  • Any embedded systems engineer or technician with the above prerequisites.
  • The prerequisites indicated above are assessed before the training by the technical supervision of the traineein his company, or by the trainee himself in the exceptional case of an individual trainee.
  • Trainee progress is assessed in two different ways, depending on the course:
    • For courses lending themselves to practical exercises, the results of the exercises are checked by the trainer while, if necessary, helping trainees to carry them out by providing additional details.
    • Quizzes are offered at the end of sections that do not include practical exercises to verifythat the trainees have assimilated the points presented
  • At the end of the training, each trainee receives a certificate attesting that they have successfully completed the course.
    • In the event of a problem, discovered during the course, due to a lack of prerequisites by the trainee a different or additional training is offered to them, generally to reinforce their prerequisites,in agreement with their company manager if applicable.

Course Outline

  • Reminder on digital electronic
  • Structure of an Integrated Circuit
  • SSI (small scale integration), TTL
  • MSI (medium scale integration), PALs, GALs, PLDs
  • LSI (large scale integration), CPLDs
  • VLSI (very large scale integration), ASICs, ASSPs, FPGAs
  • Logical architectures evolution
  • The various components
  • Technologies available on the market
  • Technology constraints
  • Interconnection methods (SRAM, Fuse, AntiFuse, Flash)
  • Clock distribution
  • Logic element types
  • Timing issues
  • Interest of HDL programming
    • VHDL
    • Verilog
  • Different steps of the design
    • Programming
    • Simulation
    • Synthesis
    • Mapping
    • Place and Route
    • Timing Analysis
    • Bitstream generation
  • Definition of a project
  • Structure of a program
  • Allocation of PIN-OUT
  • Programming
Exercise:  Understanding the steps of design and programming:
•  Getting started with the ISE IDE
•  Creating a project from scratch
•  Synthesis, Translate
•  Map
•  Place and Route (PAR)
•  BitGen
•  Report Analysis
•  Assigning I/O locations using Planahead (editing constraint file)
•  Schematics
•  Analyzing the placement
•  Flashing with Impact
  • The schematic capture
  • Primitives and symbols definition
  • Resources definition
  • Compilation
Exercise:  Developing a new IP with the Schematic Editor, Designing a Bound Detector
  • Entity/ Architecture and Module
  • Signals and wires
  • Processes and Always/Initial statements
  • Connecting existing IPs together
Exercise:  Adding a 7-Segment Display to your design
  • HDL instructions specific to simulation
  • Functional and behavioral simulation (with delays)
  • Test vector generation
Exercise:  Getting started with the ISIM simulator, developing a tesbench and simulating the previous designs
Duration
2 days
Inquiry

This course can be scheduled upon request. Click the 'Inquire' button to contact us.

More

To book a training session or for more information, please contact us on info@ac6-training.com.

Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.

You can also fill and send us the registration form

This course can be provided either remotely, in our Paris training center or worldwide on your premises.

Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 1 week before the course start.

Last update of course schedule: 23 February 2026

Booking one of our trainings is subject to our General Terms of Sales

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