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MCF5x07 implementation

This course covers MCF5307 and MCF5407 ColdFire MCUs

Objectives

  • The course describes the ColdFire assembly language and highlights differences from 68K instructions.
  • An example of SDRAM controller initialization is provided.
  • Interfacing with external devices is explained.
  • The interrupt controller is viewed in detail.
  • Interrupt driven DMA transfers are studied.
  • A programming example has been developped for each internal peripheral (serial; I2C, timer).

  • This course has been delivered several times to companies developing industrial and avionics systems.
A lot of programming examples have been developed by ACSYS to explain the boot sequence and the operation of peripherals.
•  They have been developed with Diab Data compiler and are executed under Lauterbach debugger.
A more detailed course description is available on request at training@ac6-training.com
  • Experience of a 32 bit processor or DSP is mandatory.
  • Theoretical course
    • PDF material in English (printed for face-to-face); online over Teams.
    • Trainer assistance throughout.
  • Each session starts with a trainee check-in.
  • Any embedded systems engineer or technician with the above prerequisites.
  • Prerequisites are checked before the course starts, against the prerequisites published on this page.
  • Throughout the course, learning is assessed continuously: end-of-section quizzes and direct observation by the trainer.
  • At the end of the course, each participant receives a training completion certificate.

Course Outline

  • Coldfire roadmap
  • Differences between ColdFires and 68K processors
  • 5307 block diagram
  • Pinout
  • Memory mapped I/O organization
  • 5307 pipeline
  • Programming model
  • Addressing modes
  • Instruction set
  • Stack management, subroutine call and return
  • C to assembly interface
  • Exception management
  • Internal SRAM
  • 5307 cache operation
  • Intrusive vs non-intrusive debug
  • BDM port
  • Hardware breakpoints
  • Trace port
  • Dynamic bus sizing
  • Address decoding
  • Arbitration
  • Burst cycles
  • Bus error management
  • The interrupt controller
  • The software watchdog
  • Reset, self-configuration
  • Clock synthesis
  • General Purpose I/O pins
  • SRAM connection, chip-select programming
  • DRAM / SDRAM basics
  • The 5x07 (S)DRAM controller : address decoding, refresh rate definition, address multiplexing selection
  • Asynchronous ports
  • Transmit and receive sequences
  • Synchronous port : I2C basics
  • Transmit and receive sequences
  • Single address vs dual address transfers
  • Hardware interface, hardware initiated transfers
  • Programming model
  • Capture mode
  • Period selection
  • Interrupt control
  • V4 core enhancements
  • Instruction set additions
  • Enhanced memories
  • On-chip DMA and serial ports modifications
Duration
4 days
Inquiry

This course can be scheduled upon request. Click the 'Inquire' button to contact us.

Pricing

Courses are quoted individually, with no list price. The price depends on the duration, the number of participants, the delivery mode and the technical resources provided.

For more information on our pricing, see more.

More

To book a training session or for more information, please contact us on info@ac6-training.com.

Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.

You can also fill and send us the registration form

This course can be provided either remotely, in our Paris training center or worldwide on your premises.

Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 1 week before the course start.

Last update of course schedule: 7 July 2026

Booking one of our trainings is subject to our General Terms of Sales

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