| PG1 | Multicore implementation |
This course tackles multicore implementation issues
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Objectives
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- Knowledge of high-end processor cores is recommended.
- Theoretical course
- PDF course material (in English) supplemented by a printed version for face-to-face courses.
- Online courses are dispensed using the Teams video-conferencing system.
- The trainer answers trainees' questions during the training and provide technical and pedagogical assistance.
- At the start of each session the trainer will interact with the trainees to ensure the course fits their expectations and correct if needed
- Any embedded systems engineer or technician with the above prerequisites.
- The prerequisites indicated above are assessed before the training by the technical supervision of the traineein his company, or by the trainee himself in the exceptional case of an individual trainee.
- Trainee progress is assessed by quizzes offered at the end of various sections to verify that the trainees have assimilated the points presented
- At the end of the training, each trainee receives a certificate attesting that they have successfully completed the course.
- In the event of a problem, discovered during the course, due to a lack of prerequisites by the trainee a different or additional training is offered to them, generally to reinforce their prerequisites,in agreement with their company manager if applicable.
Course Outline
- AMP
- SMP
- BMP
- Applications examples (MPC8641D, MPC8572, Virtex-4, Virtex 5)
- Exclusive resource management
- MMU page descriptor table, PowerPC tlbsync instruction
- Multi-core interrupt controller
- Inter-Processor Interrupts
- Message passing
- System booting
- Defining shared resources and non-shared resources
- Assigning a number to each core
- Dispatching tasks to a particular core, static approach, dynamic approach
- I/O management, consequence on driver design
- Software coherency (Power instructions dcbz, dcbf, dcbi, icbi)
- Hardware coherency : snooping
- Distinguishing two types of cache enabled area : random access vs sequential access, NUMA model
- PLB basics
- Exclusive resource management, lwarx/stwcx.
- Implementing a multi-core interrupt controller
- Synchronizing time bases
- Is SMP possible in a multi-405 FPGA ?
Duration
2 days
Cost
1450 € HT
Calendar
To book a training session or for more information, please contact us on info@ac6-training.com.
Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.
You can also fill and send us the
registration form
This course can be provided either remotely, in our Paris training center or, worldwide, on your premises.
Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 2 working days before the course start (1 week for face-to-face courses).
Booking one of our trainings is subject to our
General Terms of Sales
