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CYCLONE−V CORTEX−A9 HARD PROCESSOR SYSTEM

Lattice Mico32 FPGA embedded processor

Lattice Diamond

Xilinx − Microblaze implementation

Zynq All Programmable SoC: Hardware and Software Design

Microchip SmartFusion2 Programming

RISC−V Architecture

Programmable component fundamentals

VHDL Language Basics

Advanced VHDL for FPGA

Design with SystemC

ac6 >> ac6-training >> Programming >> Logique Programmable

Logique Programmable

Programmation et mise en oeuvre d'électronique programmable

La réalisation de systèmes embarqués combine de plus en plus de l'électronique programmable et du logiciel. Ces deux composantes du système contribuent de façon critique au bon fonctionnement du système et doivent être conçues et maîtrisées non seulement séparément mais également dans leurs interactions. ac6-formation propose des formations pratiques pour vous permettre de maîtriser la mise en oeuvre de composants de logique programmable et leur interactions avec la composante logicielle de vos systèmes.

You can see detailed course descriptions of the various trainings by using the above navigation bar. You can also click on course identifiers in the following course briefs hereafter.

ALT1 - CYCLONE-V CORTEX-A9 HARD PROCESSOR SYSTEM This course covers the hard IPs present in Cyclone-V Intel (Altera) FPGA family, based on ARM Cortex-A9 CPU
H1 - Lattice Mico32 FPGA embedded processor Implementing and programming a processor core in an FPGA
H2 - Lattice Diamond Mastering Diamond for FPGA optimisation and debug
HX4 - Xilinx - Microblaze implementation This course explains how to design a SoC based on MicroBlaze, Xilinx proprietary IPs and/or custom IPs using EDK
HX5 - Zynq All Programmable SoC: Hardware and Software Design This course explains how to design a System on Chip (SoC) based on the Zynq-7000 All Programmable SoC
MSP - Microchip SmartFusion2 Programming This course describe the Microcontroller Subsystem (MSS) of SmartFusion2 Microchip FPGAs
RV1 - RISC-V Architecture This course covers and explains the implementation of the RISC-V CPU

This course provides a comprehensive overview of the RISC-V architecture and instruction set for attendees. They will learn the basics of RISC-V, including RISC-V Assembler and Simulator, writing and running assembly code, and RISC-V C Programming. The course covers topics such as interrupt and exception handling, memory management, multiprocessing and concurrency, performance optimization, hardware and system design, and future developments. Hands-on experience will be provided through lab sessions.

V0 - Programmable component fundamentals This training is intended to professional who want to use or maintain programmable components

This training is intended to professional who want to use or maintain programmable components

V1 - VHDL Language Basics FPGA Programming and Simulation with VHDL
V2 - Advanced VHDL for FPGA Acquire a strong design methodology with the best of VHDL for simulation and synthesis
V3 - Design with SystemC System Design and Simulation with SystemC