FM5 MPC5674F implementation

This course covers NXP Qorivva MPC5673F and MPC5674F

Objectives
  • This course has 6 main objectives:
    • Detailing the hardware implementation of the MPC56XX
    • Parameterizing the internal interconnect and sophisticated eDMA controllers
    • Focusing on the various operation modes supported by the eQADC
    • Describing the timer units, including eTPU2
    • Describing the communication interfaces, including FlexCAN and FlexRay
    • Studying the debug capabilities offered by the Nexus interface.

  • Products and services offered by AC6:
    • AC6 is able to assist the customer by providing consultancies
    • Typical expertises are done during board bringup, hardware schematics review, software debugging, performance tuning.
A lot of programming examples have been developed by AC6 to explain the boot sequence and the operation of complex peripherals.
They have been developed with Diab Data compiler and are executed with TRACE32 Lauterbach debugger.

A more detailed course description is available on request at training@ac6-training.com
This document is necessary to tailor the course to specific customer needs and to define the exact schedule.
  • Experience of a 32-bit processor or DSP is mandatory.
  • Note that the e200z7 Power core is covered in a separate course reference FCC3 - e200z7 implementation course.
  • The following courses could be of interest:
  • Theoretical course
    • PDF course material (in English) supplemented by a printed version for face-to-face courses.
    • Online courses are dispensed using the Teams video-conferencing system.
    • The trainer answers trainees' questions during the training and provide technical and pedagogical assistance.
  • At the start of each session the trainer will interact with the trainees to ensure the course fits their expectations and correct if needed
  • Any embedded systems engineer or technician with the above prerequisites.
  • The prerequisites indicated above are assessed before the training by the technical supervision of the traineein his company, or by the trainee himself in the exceptional case of an individual trainee.
  • Trainee progress is assessed by quizzes offered at the end of various sections to verify that the trainees have assimilated the points presented
  • At the end of the training, each trainee receives a certificate attesting that they have successfully completed the course.
    • In the event of a problem, discovered during the course, due to a lack of prerequisites by the trainee a different or additional training is offered to them, generally to reinforce their prerequisites,in agreement with their company manager if applicable.

Course Outline

  • Compatibility with MPC55XX family
  • Memory mapping
  • e200z7 core integration
  • Power management controller
  • Reset
  • Clocking
  • Boot assist module (BAM)
  • Pad configuration control for each pad
  • System reset monitoring and generation
  • External interrupt pins
  • General Purpose Input Output setting
  • Internal peripheral multiplexing
  • Multiplexed address/data transfers
  • Chip-select programming
  • Burst support
  • Dynamic calibration with up to 4 chip-selects
  • 64 analog channels, differential conversions
  • ADC clock and conversion speed
  • ADC calibration feature
  • MAC unit and operand data format
  • Variable gain amplification
  • CFIFO0 streaming mode
  • 8 decimation filters
  • Temperature sensor
  • Time stamp information
  • Trigger sources
  • External multiplexing
  • Interrupt or DMA request generation
  • Crossbar switch
  • Peripheral Bridge
  • Memory Protection Unit
  • Status information regarding platform memory errors
  • 256-KB on-chip SRAM
  • 4-MB on-chip flash
  • Priority-based preemptive scheduling
  • Preemptive prioritized interrupt requests to processor
  • Software-configurable priorities of ISR or tasks
  • Software vector mode vs hardware vector mode
  • DMA request assignments
  • Transfer control descriptors
  • Channel-to-channel linking mechanism
  • Peripheral-paced hardware requests
  • Channel arbitration
  • Scatter/gather DMA processing
  • Modulo feature
  • Introduction to LIN specification
  • Idle line detection
  • LIN master node functionality
  • Detection of bit errors, physical bus errors and checksum errors
  • DMA support for both transmit and receive data
  • Hardware interface
  • 64 message buffers of zero to eight bytes data length
  • Individual Rx mask registers per message buffer
  • Powerful Rx FIFO ID filtering
  • Management of remote frames, overload frames
  • Listen-only mode capability
  • Time stamp based on 16-bit free-running timer
  • Serial Peripheral Interface (SPI) configuration
  • Deserial Serial Interface (DSI) configuration
  • Combining Serial Interface (CSI) configuration
  • Enhanced Deserial Serial Interface (DSI) configuration
  • Queued operation
  • Hardware interface
  • FlexRay memory layout
  • Message buffer concept
  • Buffer locking scheme
  • Message buffer states
  • Individual message buffer reconfiguration supported
  • Filtering on FrameID, ChannelID, MessageID
  • Slot error counters
  • System Timer Module
  • Periodic Interrupt Timer, Real Timer Interrupt
  • SWT
  • Shared time bases with the eTPU
  • Output Pulse Width Modulation (OPWM) mode
  • Input Pulse-Width Measurement (IPWM) mode
  • Pulse/Edge Accumulation (PEA) mode
  • Quadrature decode (QDEC) mode
  • Windowed Programmable Time Accumulation (WPTA) mode
  • Output Pulse Width and Frequency Modulation (OPWFM) mode
  • Pulse-Width and Frequency Modulation Buffered (OPWFMB) mode
  • Center Aligned Output Pulse Width Modulation with Dead Time (OPWMC) mode
  • Center-Aligned Output PWM Buffered with Dead Time (OPWMCB) mode
  • Hardware interface
  • Time base
  • Event-triggered microengine
  • Functions and threads
  • Host interface
  • Scheduling channel service requests
  • Parameter sharing and coherency
  • Implementing functions developed by NXP
  • Introduction to NEXUS specification
  • Data trace via data write messaging and data read messaging
  • Ownership trace via ownership trace messaging
  • Program trace via branch trace messaging
  • Watchpoint messaging via the auxiliary port
  • Run-time access to the on-chip memory