PDF course material (in English) supplemented by a printed version for face-to-face courses.
Online courses are dispensed using the Teams video-conferencing system.
The trainer answers trainees' questions during the training and provide technical and pedagogical assistance.
At the start of each session the trainer will interact with the trainees to ensure the course fits their expectations and correct if needed
Any embedded systems engineer or technician with the above prerequisites.
The prerequisites indicated above are assessed before the training by the technical supervision of the traineein his company, or by the trainee himself in the exceptional case of an individual trainee.
Trainee progress is assessed by quizzes offered at the end of various sections to verify that the trainees have assimilated the points presented
At the end of the training, each trainee receives a certificate attesting that they have successfully completed the course.
In the event of a problem, discovered during the course, due to a lack of prerequisites by the trainee a different or additional training is offered to them, generally to reinforce their prerequisites,in agreement with their company manager if applicable.
Course Outline
States and modes
Benefit of register banking
Exception mechanism
Instruction sets
Slave and master AXI ports
Highlighting the new features with regard to Cortex-R4
ARMv7-R architecture
Exceptions
System control coprocessor
Configurable options
Redundant CPU vs Twin-CPU
Prefetch unit
Instruction cycle timing and interlock behavior
Dynamic branch prediction mechanism: global history buffer
Data Processing Unit
Limited dual-issuing
Global History Buffer
Return stack
Explaining issues when several processors share an exclusive resource
Software aspects, load / store exclusive instructions
Integrated local monitor
Hardware aspects
Using events to avoid to consume power while waiting for resource release
Device and normal memory ordering
Memory type access restrictions
Access order
Memory barriers
ARM v7 PMSA
Default memory map
Cortex-R5 MPU and bus faults
Region overview
Setting up the MPU
Low Interrupt Latency
Primecell VIC PL192
VIC basic signal timing
Connectivity: daisy-chained VIC
Interrupt priority and masking
Determining the cause of the fault through CP15 status registers
Precise vs imprecise faults
Cache basics
Tag RAM and Data RAM organization
Handling cache parity / ECC errors
Cache maintenance operations
Tightly Coupled Memories
ECC/parity protection
Preloading TCMs with ECC
Using TCMs from reset
Store buffer, merging data
Hardware coherency vs software coherency
ACP pass through interface,
Virtual AXI peripheral interface region
DMA into TCM
Highlighting the difference between the µSCU and the Cortex-A SCU
PL301 AXI interconnect
AXI channels, channel handshake
Transaction ordering
Read and write burst timing diagrams
AXI master interface attributes
Write merging example
AXI slave interfaces attributes
Peripheral interfaces port attributes
Accelerator Coherency Port interface
Controlling an external cache
Clock domains
Reset domains
Power control
Maintaining caches and TCM powered while turning off the pipeline: dormant mode
Power mode interaction with ACP
Debugging the processor while powered down
Second-level address decoding
Pinout
APB3.0 new features
Event counting
Related interrupts
Debugging a multi-core system with the assistance of the PMU
Voltage domains
Run mode, standby mode, dormant mode
Communication to the power management controller
Benefits of CoreSight
Invasive debug, non-invasive debug
APBv3 debug interface
Connection to the Debug Access Port
Process related breakpoint and watchpoint
Debug Communication Channel
ETM interface
Cross-Trigger Interface
Debugging systems with energy management capabilities
Introduction
General points on syntax
Data processing instructions
Branch and control flow instructions
Memory access instructions
If…then conditional blocks
Stack in operation
Exclusive load and store instructions
Memory barriers and synchronization
Interworking ARM and Thumb states
To book a training session or for more information, please contact us on info@ac6-training.com.
Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.
This course can be provided either remotely, in our Paris training center or, worldwide, on your premises.
Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 2 working days before the course start (1 week for face-to-face courses).