This one-day course has been designed to meet the pre-requisites of ARM11 and Cortex-A/R courses. This is a summary of ARM7/9 course.
Theoretical course
PDF course material (in English) supplemented by a printed version for face-to-face courses.
Online courses are dispensed using the Teams video-conferencing system.
The trainer answers trainees' questions during the training and provide technical and pedagogical assistance.
At the start of each session the trainer will interact with the trainees to ensure the course fits their expectations and correct if needed
Any embedded systems engineer or technician with the above prerequisites.
The prerequisites indicated above are assessed before the training by the technical supervision of the traineein his company, or by the trainee himself in the exceptional case of an individual trainee.
Trainee progress is assessed by quizzes offered at the end of various sections to verify that the trainees have assimilated the points presented
At the end of the training, each trainee receives a certificate attesting that they have successfully completed the course.
In the event of a problem, discovered during the course, due to a lack of prerequisites by the trainee a different or additional training is offered to them, generally to reinforce their prerequisites,in agreement with their company manager if applicable.
Course Outline
ARM operation modes
The ARM registers set, register organization summary according to the current mode
Program Status Registers
Exception handling, vector table, automatic switch into ARM mode
Conditional execution and flags
Branch instructions
The barrel shifter
Immediate constants
Single register data transfer
Stack management
Register access in Thumb
ARM architecture V5TE new instructions
Switching between states
Mixing ARM and Thumb subroutines
ARM to thumb veneer
Thumb-to-ARM veneer
Interworking calls
Exception priority
Vector table instructions
Chaining exception handlers
FIQ vs IRQ
Example C interrupt handler
Issues when reenabling interrupts
C nested interrupt example
Data abort with memory management
Adjusting the return address
Introduction to page management
Translation Lookaside Buffer
Benefits of Fast Context Switch Extension
ARM926 MMU
Organization of page descriptor tables
Configuration & control through CP15
Cache basics
Hit under miss and its consequence: out of order abort
Highlighting data flows between main memory and caches
Write buffer
Tightly coupled memories
To book a training session or for more information, please contact us on info@ac6-training.com.
Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.
This course can be provided either remotely, in our Paris training center or, worldwide, on your premises.
Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 2 working days before the course start (1 week for face-to-face courses).