This course covers the Cortex-M1 ARM core targetting FPGA SoCs
Objectives
This course is split into 3 important parts:
Processor architecture
Software implementation
Hardware implementation.
A tutorial has been developed by ACSYS to facilitate the understanding of Cortex-M1 low level programming, therefore labs can be replayed after the course.
The course explains how to design a SoC based on Cortex-M1, clarifying the operation of the interconnect and the debug facilities integrated in the CPU.
This course does not include chapters on low level programming.
ACSYS offers a large set of tutorials to become familiar with RVDS, assembly level programming, compiler hints and tips.
More than 12 correct answers to Cortex-R prerequisites questionnaire.
Theoretical course
PDF course material (in English) supplemented by a printed version for face-to-face courses.
Online courses are dispensed using the Teams video-conferencing system.
The trainer answers trainees' questions during the training and provide technical and pedagogical assistance.
At the start of each session the trainer will interact with the trainees to ensure the course fits their expectations and correct if needed
Any embedded systems engineer or technician with the above prerequisites.
The prerequisites indicated above are assessed before the training by the technical supervision of the traineein his company, or by the trainee himself in the exceptional case of an individual trainee.
Trainee progress is assessed by quizzes offered at the end of various sections to verify that the trainees have assimilated the points presented
At the end of the training, each trainee receives a certificate attesting that they have successfully completed the course.
In the event of a problem, discovered during the course, due to a lack of prerequisites by the trainee a different or additional training is offered to them, generally to reinforce their prerequisites,in agreement with their company manager if applicable.
Course Outline
Programmer's model
Fixed memory map
Privilege, modes and stacks
Memory Protection Unit
Interrupt handling
Nested Vectored Interrupt Controller [NVIC]
Power management
Debug
Datapath and pipeline
Write buffer
Bit-banding
System timer
State, privilege and stacks
System control block
Different level of debug implementation
Exception behavior, exception return
Non-maskable exceptions
Privilege, modes and stacks
Fault escalation
Vector table
Data processing instructions
Branch and control flow instructions
Memory access instructions
Exception generating instructions
If...then conditional blocks
Exclusive load and store instructions
Accessing special registers
Memory barriers and synchronization
Interrupt entry / exit, timing diagrams
Tail chaining
Interrupt response, pre-emption
Interrupt prioritisation
Interrupt implementation configurability, impact on core size
Memory types, restriction regarding load / store multiple
This course can be provided either remotely, in our Paris training center or, worldwide, on your premises.
Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 2 working days before the course start (1 week for face-to-face courses).