PDF course material (in English) supplemented by a printed version for face-to-face courses.
Online courses are dispensed using the Teams video-conferencing system.
The trainer answers trainees' questions during the training and provide technical and pedagogical assistance.
At the start of each session the trainer will interact with the trainees to ensure the course fits their expectations and correct if needed
Any embedded systems engineer or technician with the above prerequisites.
The prerequisites indicated above are assessed before the training by the technical supervision of the traineein his company, or by the trainee himself in the exceptional case of an individual trainee.
Trainee progress is assessed by quizzes offered at the end of various sections to verify that the trainees have assimilated the points presented
At the end of the training, each trainee receives a certificate attesting that they have successfully completed the course.
In the event of a problem, discovered during the course, due to a lack of prerequisites by the trainee a different or additional training is offered to them, generally to reinforce their prerequisites,in agreement with their company manager if applicable.
Course Outline
States and modes
Benefit of register banking
Exception mechanism
Instruction sets
Purpose of CP15
Block diagram
Slave and master AXI ports
Highlighting the new features with regard to Cortex-R4/R5
ARMv7-R architecture
Operating modes
Supported instruction sets
Program Status register
Exceptions
System control coprocessor
Configurable options
Implementing two CPUs
Cache coherency using the SCU
Accelerated Coherency Port
Redundant CPU vs Dual CPU
Split/Lock configuration
Hardware coherency
SCU implementation
The MESI and MOESI protocols
ACP interface, providing hardware coherency for DMA accesses
PMU related events
Prefetch unit
Studying how instructions are processed step by step
Instruction cycle timings and interlock behavior
Dynamic branch prediction mechanism: global history buffer
Guidelines for optimal performance
Data Processing Unit
Multiple issuing
Global History Buffer
Return stack
Instruction Memory Barrier
Prefetch queue flush
PMU related events
Memory types, restriction regarding load / store multiple
Device and normal memory ordering
Memory type access restrictions
Access order
Memory barriers, self-modifying code
Memory protection overview, ARM v7 PMSA
Default memory map
Cortex-R7 MPU and bus faults
Fault status and address registers
Region overview, memory type and access control, sub-regions
This course can be provided either remotely, in our Paris training center or, worldwide, on your premises.
Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 2 working days before the course start (1 week for face-to-face courses).