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VME

This course covers VME bus, including 2eSST

Objectives

  • This course is based on the ANSI-VITA 1 1994 specification and ANSI-VITA 1.1 extensions.
  • The new 2eSST protocol is also described.
  • The training highlights synchronization methods like mailbox generally used in VME based calculators.
  • The daisy-chain acknowledge mechanism is viewed in detail.
  • Shared resource management is also emphasized.
  • The training shows how to configure a VME backplane.
  • After having reminded the 68K interrupt management, the VME priority interrupt bus is described.
  • VME timing diagrams are studied with the assistance of the VSYSTEMS analyser board.
  • The course focuses on the configuration space specified in the VME64 and VME64x standards.

  • This course has been delivered several times to companies developing defence and avionics equipments.
A more detailed course description is available on request at training@ac6-training.com
  • Experience of a parallel digital bus is recommended.
  • Theoretical course
    • PDF material in English (printed for face-to-face); online over Teams.
    • Trainer assistance throughout.
  • Each session starts with a trainee check-in.
  • Any embedded systems engineer or technician with the above prerequisites.
  • Prerequisites are checked before the course starts, against the prerequisites published on this page.
  • Throughout the course, learning is assessed continuously: end-of-section quizzes and direct observation by the trainer.
  • At the end of the course, each participant receives a training completion certificate.

Course Outline

  • VME based calculator architecture
  • Connectors pinout
  • The four bus parts
  • Explanation of the daisy-chain acknowledge mechanim
  • RRS, PRI and ONE Arbiter options
  • RWD, ROR, FAIR requester options
  • Arbitration sequence analysis
  • Byte locations accessed during a data transfer
  • Address pipelining
  • Burst transfers
  • Address Only transactions
  • BTO timer utility
  • Shared resource management
  • Interrupt generator structure
  • Interrupt handler structure
  • Status/ID read cycle
  • ROAK and RORA interrupt generator options
  • SYSFAIL management
  • Reset timing diagram
  • Power control
  • Auto system controller
  • The 5 signal types
  • Bus driving and receiving requirements
  • Noise margins
  • Board powering, current ratings for power pins
  • Line terminations
  • The ETL transceiver logic required for 2eSST
  • Determination of the mapping of the A24 config space
  • Detail of the CR and CSRs
  • Auto slot ID mechanism
  • New P0/J0 connector
  • P1/J1, P2/J2 connectors pinouts, rows z and d pin assignments
  • Live insertion support
  • EMC front panel and subracks
  • ESD protection
  • ETL technology
  • 2eVME protocol
  • 3U and 6U implementations
  • Broadcast transfers
  • Source synchronous transfers, data centered strobes
  • Skew calculation
Duration
4 days
Inquiry

This course can be scheduled upon request. Click the 'Inquire' button to contact us.

Pricing

Courses are quoted individually, with no list price. The price depends on the duration, the number of participants, the delivery mode and the technical resources provided.

For more information on our pricing, see more.

More

To book a training session or for more information, please contact us on info@ac6-training.com.

Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.

You can also fill and send us the registration form

This course can be provided either remotely, in our Paris training center or worldwide on your premises.

Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 1 week before the course start.

Last update of course schedule: 27 June 2026

Booking one of our trainings is subject to our General Terms of Sales

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