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ac6 >> ac6-training >> Programmation >> Logique Programmable >> Advanced VHDL for FPGA Télécharger le catalogue Télécharger la page Ecrivez nous Version imprimable

V2 Advanced VHDL for FPGA

Acquire a strong design methodology with the best of VHDL for simulation and synthesis

formateur
Objectives
  • Take the best of VHDL language for logical synthesis and simulation
  • Implementing combinational and sequential logic
  • Developing Finite State Machines
  • Organizing the code developing package and libraries
  • Reusing components
  • Learning how to write efficient test benches for simulation
  • Knowing the different writing style and their impact on the quality of synthesis results
  • Checking Timings
  • Synthesis and Place & Route results parameterizing
Course environment
  • A PC in pairs
  • Xilinx ISE Design Suite v.14.7 IDE / Xilinx Vivado v.2013.4 IDE
  • Nexys-3 (Xilinx Spartan6-based) board / Nexys-4 (Xilinx Artix7-based) board
Prerequisites
  • Knowledge of digital technology
  • Basic knowledge of the VHDL language

First day
Reminders
  • Summary of VHDL
  • DATA types
    • Categories of types
    • Predefined and standard Types
    • Types and packages
    • Converting between types
  • Design Units
    • Entity declaration
    • Architecture body
    • Package declaration and package body
  • Statements Declaration and Expression
    • Scope visibility and Overloading
    • use Clause
    • Static versus Dynamic Expressions
  • Operators operands and attributes
  • Statements
    • Concurrent Statements
    • Sequential Statements
    • Assignment statements
Exercise :  Bounds Checker
Exercise :  Synchronous logic and variables
Exercise :  Combinational and synchronous processes, loops, variables and registers
Second day
Synthesis and Testbenches
  • Synthesis
    • Syntactic and Semantic Restriction
    • Creating synthesizable Designs
    • Inferring Hardware elements
    • Initialization and Reset
    • Pragmas
  • Testbenches
    • Introduction
    • Testbench for a Combinational Circuit
    • Testbench for a clocked Circuit
    • Testbench with File I/O
    • Random Stimulus and functional Coverage
Exercise :  Synchronous logic and storage
Exercise :  Simulation of sequential processes
Exercise :  Advanced simulation techniques Text files
Finite State Machines
  • Finite State Machines
  • Describing a FSM in VHDL
  • Reset of a FSM
  • Moore's and Mealy's outputs
  • State Encoding
Exercise :  Burstable RAM controller
Exercise :  Enhanced FSM
Hierarchical Design and Code Reuse
  • Hierarchical Design
    • Genericity
    • Components
    • Configurations
  • Generation Statements
  • Functions and Procedures
  • Aliases
  • Packages
Exercise :  Genericity and hierarchical design
Exercise :  Configurations
Exercise :  Packages
Exercise :  Modeling Memory
Third day
Design Methodology for Synthesis
  • Designing for Synthesis
  • Metastability
  • Memory Synthesis
  • Reset Generation
  • Crossing Clock domains
Exercise :  Metastability
Timing Analysis
  • Timing Paths
  • Setup Analysis
  • Hold Analysis
  • Other path type
Exercise :  Design closure
Exercise :  Analyzing and Resolving timing violations
Fourth day
Advanced VHDL features for optimization and code reuse in logical synthesis
  • Hierarchical division
  • Package and Use Clause
    • Package Declarations
    • Package Bodies
    • Use Clauses
    • Context Declarations and Use
  • Libraries
Exercise :  Creating Package and Libraries and working with them
  • Genericity and automatic configuration of re-usable modules
    • Generic Constants, Generic Types, Generic Lists
    • Generic Subprograms, Generic Packages
Exercise :  Enhancing a 4-bit BCD-counter/decounter to create a generic one
  • Components and Configurations
    • Components
    • Configuring components instances
    • Direct instantiation
    • Basic configurations
    • Multiple levels Configuration
Exercise :  Working with configurations
  • Generate statements
    • Generating Iterative Structures
    • Conditionally Generating Structures
    • Configuration of Generate statement
  • Concurrent instructions “for generate “
Exercise :  Designing a n digits BCD-counter/decounter and displaying it on a 7-segment display
Vivado Debug
  • Vivado Integrated Logic Analyzer (ILA)
  • Adding debug nets
  • Analyzing debug data
  • Resources