FC3

MPC744X/5X implementation

This course covers NXP G4+ Power CPU, including MPC7448

Objectives

  • The course provides coding guidelines based on the knowledge of the instruction pipeline.
  • Alignment rules are to be determined to avoid cache replacement of data being processed.
  • Data flows between SDRAM, L1 caches , L2 and possibly L3 cache are highlighted.
  • MESI cache coherency protocol is introduced in increasing depth.
  • Vector instructions and new C operators are viewed in detail.
  • Data streams parameterizing is emphasized through an example.
  • This course covers bus operation in either 60X or MPX mode.
  • Through a FIR algorithm, the instructor shows how to vectorize processing and reduce execution time using data streaming.
  • The internal performance monitor has been programmed so that different versions of the FIR algorithm implementation can be compared.
  • This course has been delivered several times to companies involved in the design of avionics equipments, such as flight controller.
A more detailed course description is available on request at training@ac6-training.com
  • Experience of a 32 bit processor or DSP is mandatory.
  • Theoretical course
    • PDF material in English (printed for face-to-face); online over Teams.
    • Trainer assistance throughout.
  • Each session starts with a trainee check-in.
  • Any embedded systems engineer or technician with the above prerequisites.
  • Prerequisites are checked before the course starts, against the prerequisites published on this page.
  • Throughout the course, learning is assessed continuously: end-of-section quizzes and direct observation by the trainer.
  • At the end of the course, each participant receives a training completion certificate.

Course Outline

  • Pipeline basics
  • 744X/5X pipeline implementation
  • Issue queue resource requirements
  • Execution model
  • Dispatch conditions, completion conditions
  • Execution serialization
  • Branch management
  • Guarded memory
  • Cache basics
  • 744X/5X L1 cache
  • Transient load instructions benefits
  • L2 cache organization
  • L2 replacement algorithm selection, L2 locking
  • L3 Cache organization according to L3 size
  • L3 replacement algorithm selection, L3 locking
  • L3 SSRAM used as private memory
  • Cache coherency basics
  • The MESI L1 data line states
  • MESI snooping sequences involving 2 G4 and a PCI master
  • L1 and L2 cache loading, hit under miss
  • The MSS [Memory Sub System]
  • The load fold queue
  • The store miss merging advantage
  • Purpose of sync and eieio instructions
  • The 3 architecture layers introduction : UISA, VEA and OEA
  • Low power modes
  • Performance monitor
  • JTAG debugger
  • Real time trace
  • Differences between 7441, 7445, 7450, 7451, 7455, 7447, 7457 and 7448
  • Branch instructions
  • Integer load / store instructions
  • Integer arithmetic and logic instructions
  • IEEE754 basics
  • Float load / store instructions
  • Float arithmetic instructions
  • The EABI
  • Cache related instructions
  • Little-endian emulation
  • PowerPC timers : TB and DEC
  • Altivec introduction, SIMD processing
  • Intra vs inter element instructions
  • Altivec registers
  • ANSI C extension to support vector operators
  • Vector load / store instructions
  • Vector integer instructions
  • Vector float instructions
  • Vector permut instructions
  • Altivec implementation on the 744X/5X
  • Data streams management
  • EABI extension to support Altivec
  • MMU goals
  • The PowerPC address processing
  • Enabling of 4 additional BAT on 7445/55
  • 32-bit or 36-bit real address size selection
  • WIMG attributes definition, page and block access rights definition
  • Process protection through VSID selection
  • TLB organization
  • Page translation
  • Software vs hardware TLB reload
  • MMU implementation in real-time sensitive applications
  • Exception management
  • Registers updating related to the exception cause
  • Requirements to support exception nesting
  • Bus interface configuration
  • Auto-check on power up
  • Pinout
  • Bus features : address pipelining, split transactions
  • 60X bus mode : address phase and data phase
  • MPX bus mode : *HIT and *DRDY pins use
  • Data only transactions
  • MPX bus cycles overview
  • Other signals : interrupts, machine check
  • Synchronous SRAMs technologies
  • L3 bus pinout, L3 clock synchronization
  • SSRAM related parameters initialization in L3CR register
Duration
5 days
Inquiry

This course can be scheduled upon request. Click the 'Inquire' button to contact us.

Pricing

Courses are quoted individually, with no list price. The price depends on the duration, the number of participants, the delivery mode and the technical resources provided.

For more information on our pricing, see more.

More

To book a training session or for more information, please contact us on info@ac6-training.com.

Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.

You can also fill and send us the registration form

This course can be provided either remotely, in our Paris training center or worldwide on your premises.

Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 1 week before the course start.

Last update of course schedule: 27 June 2026

Booking one of our trainings is subject to our General Terms of Sales

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