The course clarifies the architecture of the P20X0, particularly the operation of the coherency module that interconnects the e500s to memory and high-speed interfaces.
Cache coherency protocol is introduced in increasing depth.
The e500 core is viewed in detail, especially the SPE unit that enable vector processing.
The boot sequence and the clocking are explained.
The course focuses on the hardware implementation of the P20X0.
A long introduction to DDR SDRAM operation is done before studying the DDR2/3 SDRAM controller.
An in-depth description of the RapidIO port and the PCI-Express port is done.
The course explains how to implement QoS on GigaEthernet controllers.
ACSYS has developed an optimized SPE based FFT coded in assembler language.
Performance for 1024 complex floating point single precision samples is:
- 91_386 core clock cycles without reverse ordering, 94_124 with reverse ordering
Performance for 4096 complex floating point single precision samples is:
- 470_778 core clock cycles without reverse ordering, 511_227 with reverse ordering
Experience of a 32-bit processor or DSP is mandatory.
Knowledge of RapidIO and PCI Express is recommended.
Theoretical course
PDF course material (in English) supplemented by a printed version for face-to-face courses.
Online courses are dispensed using the Teams video-conferencing system.
The trainer answers trainees' questions during the training and provide technical and pedagogical assistance.
At the start of each session the trainer will interact with the trainees to ensure the course fits their expectations and correct if needed
Any embedded systems engineer or technician with the above prerequisites.
The prerequisites indicated above are assessed before the training by the technical supervision of the traineein his company, or by the trainee himself in the exceptional case of an individual trainee.
Trainee progress is assessed by quizzes offered at the end of various sections to verify that the trainees have assimilated the points presented
At the end of the training, each trainee receives a certificate attesting that they have successfully completed the course.
In the event of a problem, discovered during the course, due to a lack of prerequisites by the trainee a different or additional training is offered to them, generally to reinforce their prerequisites,in agreement with their company manager if applicable.
Course Outline
Internal data flows, OCEAN switch fabric, packet reordering
Implementation examples
Address map, ATMU, OCEAN configuration
Local vs external address spaces, inbound and outbound address decoding
Accessing memory-mapped registers from external master
This course can be provided either remotely, in our Paris training center or, worldwide, on your premises.
Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 2 working days before the course start (1 week for face-to-face courses).