FPQ5 | MPC8309 implementation |
This course covers PowerQUICC II Pro MPC8309, MPC8306 and MPC8306S
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Objectives
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- Experience of a 32-bit processor or DSP is mandatory.
- The following courses could be of interest:
- Ethernet and switching, reference N1 - Ethernet and switching course
- IEEE1588, reference N2 - IEEE1588 - Precise Time Protocol course
- PCI, reference IC1 - PCI 3.0 course
- USB Full Speed High Speed and USB On-The-Go, reference IP2 - USB 2.0 course
- SD / MMC, reference IS2 - eMMC 5.0 course
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CAN bus, reference IA1 - CAN bus course
- Theoretical course
- PDF course material (in English) supplemented by a printed version for face-to-face courses.
- Online courses are dispensed using the Teams video-conferencing system.
- The trainer answers trainees' questions during the training and provide technical and pedagogical assistance.
- At the start of each session the trainer will interact with the trainees to ensure the course fits their expectations and correct if needed
- Any embedded systems engineer or technician with the above prerequisites.
- The prerequisites indicated above are assessed before the training by the technical supervision of the traineein his company, or by the trainee himself in the exceptional case of an individual trainee.
- Trainee progress is assessed by quizzes offered at the end of various sections to verify that the trainees have assimilated the points presented
- At the end of the training, each trainee receives a certificate attesting that they have successfully completed the course.
- In the event of a problem, discovered during the course, due to a lack of prerequisites by the trainee a different or additional training is offered to them, generally to reinforce their prerequisites,in agreement with their company manager if applicable.
Course Outline
- Internal architecture
- Highlighting data paths inside the MPC8309
- Highlighting differences between MPC8309, MPC8306 and MPC8306S
- Application examples
- Superscalar operation, out-of-order execution, register renaming, serializations, isync instruction
- Branch processing unit, prediction
- Coding guidelines
- Load / store buffers
- Sync and eieio instructions
- Store gathering mechanism
- Cache basics
- L1 caches
- Cache coherency mechanism, snooping, related signals
- Memory coherency required attribute
- The MEI state machine
- Basic snoop requests
- Management of cache enabled pages shared with DMAs
- Cache related instructions
- Software enforced cache coherency
- Cache flush routine
- PowerPC architecture specification, the 3 books UISA, VEA and OEA
- e300 registers
- Addressing modes, load / store instructions
- Floating point arithmetical instructions
- The PowerPC EABI
- Linking an application with Diab Data
- Introduction to real, block and segmentation / pagination translations
- Real mode restrictions
- Memory attributes and access rights definition
- TLBs organization
- Segment-translation
- Page-translation
- MMU implementation in real-time sensitive applications
- Critical interrupt, automatic nesting
- Exception management mechanism
- Registers updating according to the exception cause
- Requirements to allow exception nesting
- JTAG emulation, restrictions
- Hardware breakpoints
- Power management control
- Configuration signals sampled at reset
- Output signals state during reset
- Reset configuration words source
- Clocking
- Address translation and mapping
- Arbiter and bus monitor
- Timers
- Dynamic power management
- DDR-SDRAM operation
- Jedec specification basics
- On-Die termination and calibration
- Hardware interface
- Bank activation, read, write and precharge timing diagrams, page mode
- Initial configuration following Power-on-Reset
- Timing parameters programming
- Initialization routine
- Multiplexed or non-multiplexed address and data buses
- Dynamic bus sizing
- GPCM, UPMs states machines
- Nand Flash Controller
- Booting from NAND flash
- Bridge features
- Read prefetch and write posting FIFOs
- Inbound transactions handling, outbound transactions handling
- PCI bus arbitration
- Storing and executing commands targeting the external card
- Multi-block transfers
- Moving data by using the dedicated DMA controller
- Dividing large data transfers
- Card insertion and removal detection
- DMA engine 1
- Transfer control descriptor format
- Channel-to-channel linking mechanism
- Scatter/gather DMA processing
- DMA engine 2
- Data chaining and direct mode
- Priority between the 4 channels
- Definition of interrupt priorities
- System critical interrupt
- Interrupt management, vector register
- Machine check interrupts
- Hardware interface
- 64 message buffers (MB) of zero to eight bytes data length
- Individual Rx mask registers per message buffer
- Powerful Rx FIFO ID filtering
- Management of remote frames, overload frames
- Programmable transmission priority scheme
- Time stamp based on 16-bit free-running timer
- Global network time
- Dual-Role operation
- EHCI implementation
- ULPI interfaces to the transceiver
- Dedicated DMA channels
- Endpoints configuration
- DUART
- I2C controller
- SPI controller
- Serial DMA
- Multi-threading
- NMSI vs TDM
- Baud-rate generators
- QUICC engine timers
- Utilization of Buffer Descriptors
- Chaining descriptors into rings
- Frame boundary definition
- Handling UCC interrupts
- Initialization sequence
- UCC for fast protocols, virtual FIFOs
- Defining Tx- and Rx-FIFO thresholds
- Physical interfaces to transceiver
- Auto-negotiation
- IP header checksum
- Frame filtering and address recognition
- Quality of Service
- Ethernet scheduler, traffic shaper
- BD and Parameter RAM description
- Ethernet host command set
- Timestamp unit key features
- Real Time Clock
- How QuiccEngine and host software interact
- QMC and serial interface
- UCC Base and Global multichannel parameters
- Channel-specific HDLC parameters
- QMC host commands
- Introducing the tools required to generate the kernel image
- What is required on the host before installing LTIB
- Common package selection screen
- Common target system configuration screen
- Building a complete BSP with the default configurations
- Creating a Root Filesystems image
- e-configuring the kernel under LTIB
- Selecting user-space packages
- Setup the bootloader arguments to use the exported RFS
- Debugging Uboot and the kernel by using Trace32
- Command line options
- Adding a new package
- Other deployment methods
- Creating a new package and integrating it into LTIB
- A lot of labs have been created to explain the usage of LTIB