FPQ9 MPC8360E implementation

This course covers PowerQUICC II Pro MPC8360E

Objectives
  • The course explains how to optimize the internal traffics flowing through the interconnect CSB bus.
  • Cache coherency protocol is introduced in increasing depth.
  • The 32-bit e300 core is viewed in detail, especially the MMU and the cache.
  • The boot sequence and the clocking are explained.
  • The course focuses on hardware implementation of the MPC8360E.
  • A long introduction to DDR SDRAM operation is done before studying the DDR2 SDRAM controllers.
  • An in-depth description of the PCI controller is performed.
  • Two controllers present in the QuiccEngine are particularly studied : Ethernet on UCC and multi-channel, and the course explains how to implement an inter-working between TDM lines and Ethernet.
  • The course highlights both hardware and software implementation of gigabit / fast / Ethernet controllers.
  • The USB controller is also detailed.
  • Generation of a Linux image and Root File System by using LTIB can also be included into the training.

  • This course has been delivered several times to companies developing telecom infrastructure equipments.
A lot of programming examples have been developed by ACSYS to explain the boot sequence and the operation of complex peripherals, such as USB and Ethernet.
•  They have been developed with Diab Data compiler and are executed under Lauterbach debugger.
A more detailed course description is available on request at training@ac6-training.com
  • Experience of a 32 bit processor or DSP is mandatory.
  • The knowledge of the following interconnect standards may be required:
  • Cours théorique
    • Support de cours au format PDF (en anglais) et une version imprimée lors des sessions en présentiel
    • Cours dispensé via le système de visioconférence Teams (si à distance)
    • Le formateur répond aux questions des stagiaires en direct pendant la formation et fournit une assistance technique et pédagogique
  • Au début de chaque demi-journée une période est réservée à une interaction avec les stagiaires pour s'assurer que le cours répond à leurs attentes et l'adapter si nécessaire
  • Tout ingénieur ou technicien en systèmes embarqués possédant les prérequis ci-dessus.
  • Les prérequis indiqués ci-dessus sont évalués avant la formation par l'encadrement technique du stagiaire dans son entreprise, ou par le stagiaire lui-même dans le cas exceptionnel d'un stagiaire individuel.
  • Les progrès des stagiaires sont évalués par des quizz proposés en fin des sections pour vérifier que les stagiaires ont assimilé les points présentés
  • En fin de formation, une attestation et un certificat attestant que le stagiaire a suivi le cours avec succès.
    • En cas de problème dû à un manque de prérequis de la part du stagiaire, constaté lors de la formation, une formation différente ou complémentaire lui est proposée, en général pour conforter ses prérequis, en accord avec son responsable en entreprise le cas échéant.

Plan du cours

  • Highlighting data paths inside the MPC8360E
  • Block diagram : characteristics of each of the 3 internal modules e300 core, Platform, QuiccEngine
  • Software migration from MPC82XX/MPC85XX families
  • e300 pipeline
  • Branch processing unit
  • Coding guidelines
  • Load / store buffers
  • Sync and eieio instructions
  • Store gathering mechanism
  • Cache basics
  • Cache locking
  • L1 caches
  • Cache coherency mechanism
  • The MEI state machine
  • Management of cache enabled pages shared with PCI DMAs
  • Software enforced cache coherency
  • Cache flush routine
  • e300 registers
  • Addressing modes, load / store instructions
  • IEEE754 basics, floating points numbers encoding
  • Floating point load / store instructions
  • Floating point arithmetical instructions
  • The PowerPC EABI
  • Linking an application with Diab Data, parameterizing the linker command file
  • Thread vs process
  • Real mode restrictions
  • Memory attributes and access rights definition
  • Virtual space benefit
  • TLBs organization
  • Segment-translation
  • Page-translation
  • MMU implementation in real-time sensitive applications
  • Exception management mechanism
  • Registers updating according to the exception cause
  • Requirements to allow exception nesting
  • JTAG emulation, restrictions
  • Hardware breakpoints
  • Performance monitor
  • DC and AC electrical characteristics
  • Configuration signals sampled at reset
  • Reset configuration words source
  • Utilization of the I2C boot sequencer
  • PCI Host / Agent configuration
  • Boot memory space
  • Clocking in PCI Host mode, system clock domains
  • External clock inputs
  • Address translation and mapping
  • Arbiter and bus monitor
  • General purpose inputs / outputs
  • Timers
  • Dynamic power management
  • Jedec specification basics
  • On-Die termination and calibration
  • Differences between DDR1 and DDR2
  • Command truth table
  • Hardware interface
  • ECC error correction
  • DDR-SDRAM controller overview
  • Address decode
  • Timing parameters programming
  • Initialization routine
  • Multiplexed or non-multiplexed address and data buses
  • Dynamic bus sizing
  • GPCM, UPMs states machines
  • Bridge features
  • Data flows
  • Inbound transactions handling, Outbound transactions handling
  • PCI bus arbitration
  • PCI hierarchy configuration when operating as host
  • Priority between the 4 channels
  • Scatter / gathering
  • Concurrent execution across multiple channels
  • Messaging unit
  • Interrupt sources
  • Definition of interrupt priorities
  • System critical interrupt
  • Requirements to support nesting
  • Overview of the encryption mechanism
  • Introduction to DES, 3DES and AES algorithms
  • Crypto channels
  • Snooping by caches
  • Implementation of IPSEC
  • Description of the NS16450/16550 compliant Uarts
  • FIFO mode
  • Flow control signal management
  • I2C protocol fundamentals
  • Transfer timing diagrams, SCL and SDA pins
  • Transmit and receive sequence
  • Serial DMA
  • QUICC engine external requests
  • Multi-threading
  • NMSI vs TDM
  • CMX registers
  • Baud-rate generators
  • Utilization of Buffer Descriptors
  • Chaining descriptors into rings
  • Frame boundary definition
  • Interrupt management
  • Introduction to SPI protocol
  • SPI modes of operation in QUICC engine mode
  • Transmit and receive sequence
  • UCC feature set
  • Handling UCC interrupts
  • Initialization sequence
  • UCC as slow communications controllers, UART mode
  • UCC for fast protocols, virtual FIFOs
  • Physical interfaces to transceiver
  • Auto-negotiation
  • Termination and interworking modes of operation
  • IP header checksum
  • Frame filtering and address recognition
  • Header parsing
  • Quality of Service
  • Ethernet scheduler, traffic shaper
  • BD and Parameter RAM description
  • Ethernet statistics, MIB
  • Overview of the IEEE1588 standard
  • Timestamp unit key features
  • How QuiccEngine and host software interact
  • PTP frame reception
  • PTP frame transmission
  • Comparison with MPC82XX CPM MCC
  • Channel-specific HDLC parameters
  • Channel extra parameters
  • MCC exceptions
  • MCC host commands
  • QMC and serial interface
  • UCC Base and Global multichannel parameters
  • Channel-specific HDLC parameters
  • QMC exceptions
  • QMC host commands
  • Host controller limitations
  • Endpoint parameters block pointer
  • Frame number
  • USB BD ring
  • Host commands
  • Introducing the tools required to generate the kernel image
  • What is required on the host before installing LTIB
  • Common package selection screen
  • Common target system configuration screen
  • Building a complete BSP with the default configurations
  • Creating a Root Filesystems image
  • e-configuring the kernel under LTIB
  • Selecting user-space packages
  • Setup the bootloader arguments to use the exported RFS
  • Debugging Uboot and the kernel by using Trace32
  • Command line options
  • Adding a new package
  • Other deployment methods
  • Creating a new package and integrating it into LTIB
    • A lot of labs have been created to explain the usage of LTIB