STR4 STM32 F0-Series implementation

This course covers STM32F050 and STM32F051 ARM-based MCU family

Objectives

Describing the hardware implementation and highlighting the pitfalls
Describing the ARM Cortex-M0 core architecture
Becoming familiar with the IDE and low level programming
Describing the units which are interconnected to other modules, such as clocking, interrupt controller and DMA controller, because the boot program generally has to modify the setting of these units
Describing independent I/O modules and their drivers.

Note that this course has been designed from the architecture of the most complex STM32 F1-Series device, the STM32F051.
Consequently, a chapter has been designed by Acsys for each possible integrated IP.

According to the actual reference chosen by the customer, some chapters may be removed.

ACSYS is able to assist the customer by providing consultancies. Typical expertises are done during board bringup, hardware schematics review, software debugging, performance tuning.
ACSYS has also an expertise in FreeRTOS porting.

	A lot of programming examples are provided to help the attendee to become familiar with the topics taught in the course.
	Labs included in this course are conducted under the System Workbench for STM32 free IDE. For on-site courses, they can also be compiled and executed under two other IDEs: IAR and Keil
	A more detailed course description is available on request at training@ac6-training.com
	This document is necessary to tailor the course to specific customer needs and to define the exact schedule.

Prerequisites and related courses

This course provides an overview of the ARM Cortex-M0 core. Our course reference RM0 - Cortex-M0 / Cortex-M0+ implementation course details the operation of this core.

ARCHITECTURE OF STM32F0 MCUs

ARM core based architecture
Description of STM32F050X and STM32F051X SoC architecture
Clarifying the internal data and instruction paths: AHB-lite interconnect, peripheral buses, AHB-to-APB bridges
Private Peripheral Bus (PPB)
Integrated memories
SoC mapping

THE ARM CORTEX-M0 CORE

BECOMING FAMILIAR WITH THE IDE

PROGRAMMING AND DEBUGGING

RESET, POWER AND CLOCKING

INTERNAL INTERCONNECT

HARDWARE IMPLEMENTATION

INTEGRATED MEMORIES

TIMERS

ANALOG MODULES

INTEGRITY

CONNECTIVITY AND COMMUNICATION

OTHER INTERFACES

Duration	Cost	Calendar
4 days	2250 € HT
Last update: 2 May 2016
This course can be provided either remotely or in our Paris training center or, worldwide, on your premises. Scheduled classes are confirmed as soon as there is a confirmed booking.
To book a training session or for more information, please contact us on info@ac6-training.com. Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us. You can also fill and send us the registration form
Booking one of our trainings is subject to our General Terms of Sales