STR4 STM32 F0-Series implementation

This course covers STM32F050 and STM32F051 ARM-based MCU family

Objectives

This course has 5 main objectives:

Describing the hardware implementation and highlighting the pitfalls
Describing the ARM Cortex-M0 core architecture
Becoming familiar with the IDE and low level programming
Describing the units which are interconnected to other modules, such as clocking, interrupt controller and DMA controller, because the boot program generally has to modify the setting of these units
Describing independent I/O modules and their drivers.

Note that this course has been designed from the architecture of the most complex STM32 F1-Series device, the STM32F051.
Consequently, a chapter has been designed by Acsys for each possible integrated IP.

According to the actual reference chosen by the customer, some chapters may be removed.

Products and services offered by ACSYS:

ACSYS is able to assist the customer by providing consultancies. Typical expertises are done during board bringup, hardware schematics review, software debugging, performance tuning.
ACSYS has also an expertise in FreeRTOS porting.

	A lot of programming examples are provided to help the attendee to become familiar with the topics taught in the course.
	Labs included in this course are conducted under the System Workbench for STM32 free IDE. For on-site courses, they can also be compiled and executed under two other IDEs: IAR and Keil
	A more detailed course description is available on request at training@ac6-training.com
	This document is necessary to tailor the course to specific customer needs and to define the exact schedule.

Prerequisites and related courses

This course provides an overview of the ARM Cortex-M0 core. Our course reference cours RM0 - Cortex-M0 / Cortex-M0+ implementation details the operation of this core.

ARCHITECTURE OF STM32F0 MCUs

ARM core based architecture
Description of STM32F050X and STM32F051X SoC architecture
Clarifying the internal data and instruction paths: AHB-lite interconnect, peripheral buses, AHB-to-APB bridges
Private Peripheral Bus (PPB)
Integrated memories
SoC mapping

THE ARM CORTEX-M0 CORE

V6-M core family
Core architecture
Programming
Exception behavior, exception return
Basic interrupt operation, micro-coded interrupt mechanism

BECOMING FAMILIAR WITH THE IDE

Acsys covers 3 IDEs: Keil, IAR and GCC / Lauterbach
Thus the customer has just to indicate which one he has chosen

Getting started with the IDE
Parameterizing the compiler / linker
Creating a project from scratch
C start program

PROGRAMMING AND DEBUGGING

Debug interface
Programming

RESET, POWER AND CLOCKING

Power control
Reset
Clocking
Low power modes

INTERNAL INTERCONNECT

Bus matrix
DMA

HARDWARE IMPLEMENTATION

Power pins
Pinout
GPIO module
System configuration controller
External Interrupts

INTEGRATED MEMORIES

Embedded flash memory
Internal SRAM

TIMERS

Advanced-control timers TIM1
General-purpose timers (TIM2 and TIM3)
General-purpose timers (TIM14-17)
Basic timers (TIM6)
Real Time Clock
Independent Watchdog
Window Watchdog

ANALOG MODULES

12-bit Analog-to-Digital Converter and Programmable Gain Amplifier
12-bit Digital-to-Analog Converter
Comparator

INTEGRITY

CRC calculation unit

CONNECTIVITY AND COMMUNICATION

SPI
SPI in I2S mode
USART
I2C

OTHER INTERFACES

Touch sensing interface
HDMI-CEC

Ce cours peut être dispensé dans notre centre de formation près de Paris,ou dans vos locaux, en France ou dans le monde entier. Il peut aussi être dispensé sous forme d'un cours en ligne, animé par un de nos formateurs.

Nos formateurs sont bilingues et assurent le cours en français ou en anglais. Les sessions inter-entreprises programmées sont ouvertes dès deux inscrits.

Pour vous enregistrer ou pour toute information supplémentaire, contactez nous par email à l'adresse info@ac6-formation.com.

Les inscriptions aux sessions de formation sont acceptées jusqu'à une semaine avant le début de la formation. Pour une inscription plus tardive nous consulter

Vous pouvez aussi remplir et nous envoyer le bulletin d'inscription

Dernière mise à jour du plan de cours : 2 mai 2016

L'inscription à nos formations est soumise à nos Conditions Générales de Vente