oV2 VHDL Language advanced features

Objectives
  • Comprehend the various possibilities offered by VHDL language
  • Be able to read and test VHDL components
  • Understand the logical synthesis notions
  • Understand the crucial issue of implementing Finite State Machines (FSMs) in hardware
  • Organizing the code developing package and libraries
  • Reusing components
  • Learning how to write efficient testbenches for simulation
  • Knowing the different writing style and their impact on the quality of synthesis results
  • Checking Timings
  • How to structure and write large and complex VHDL structured verification environments
  • The OSVVM and UVVM VHDL verification methodologies
Prerequisites
Course environment
  • Theoretical course
    • PDF course material (in English)
    • Course dispensed using the Teams video-conferencing system
    • The trainer to answer trainees’ questions during the training and provide technical and pedagogical assistance through the Teams video-conferencing system
  • Practical activities
    • Practical activities represent from 40% to 50% of course duration
    • They allow to validate or deepen the knowledge obtained during the theoretical course
    • One Online Linux PC per trainee for the practical activities
    • Xilinx Vivado IDE
    • Code examples, exercises and solutions
    • The trainer has access to trainees’ Online PCs for technical and pedagogical assistance.
    • Some practical activities may be continued between training sessions and are checked by the trainer during the following session
  • At the start of each session, a period is devoted to an interaction between the trainees and the trainer to ensure the course fit their expectations and adapt it if needed
Duration
  • Total: 24 hours
  • 4 sessions, 6 hours each (excluding break time)
  • From 40% to 50% of training time is devoted to practical activities
  • Some Labs may be completed between sessions and are checked by the trainer on the next session

First session
Synthesis and Testbenches
  • Synthesis
    • Syntactic and Semantic Restriction
    • Creating synthesizable Designs
    • Inferring Hardware elements
    • Initialization and Reset
    • Pragmas
  • Testbenches
    • A few basic rules for the writing of an efficient test bench
    • Potential incoherencies between logical synthesis and simulation: how to avoid it
    • VHDL instructions specific to simulation
    • Testbench with File I/O
Exercise:  Designing and testing a logical address decoder
Exercise:  Simulation of sequential processes
Exercise:  Advanced simulation techniques Text files
Finite State Machine (1st part)
  • The Finite State Machine Approach
    • Sequential Circuits and State Machines
    • State Transition Diagram
    • Transition Types
    • Moore-to-Mealy Conversion
    • Mealy-to-Moore Conversion
    • Exercises
  • Hardware Fundamentals
    • Flip-Flops
    • Metastability and Synchronizers
    • Pulse Detection
    • Glitches
    • Pipelined Implementations
    • Exercises
    • Hardware Architectures for State Machines
    • Fundamental Design Technique for Moore Machines
    • Fundamental Design Technique for Mealy Machines
    • Moore versus Mealy Time Behavior
    • State Machine Categories and State-Encoding Options
    • Safe State Machines
Second session
Finite State Machine (2nd part)
  • Design Steps and Classical Mistakes
    • Classical Problems and Mistakes
    • Design Steps Summary
  • Regular State Machines
    • Architectures for Regular Machines
    • Number of Flip-Flops
    • Exercises
  • Timed State Machines
    • Architectures for Timed Machines
    • Timer interpretation
    • Transition Types and Timer Usage
    • Timer Control Strategies
    • Time Behavior of Timed Moore and Mealy Machines
    • Examples of Timed Machines
Exercise:  Designing a burstable RAM controller
Hierarchical Conception
  • Hierarchical division
  • Analysis and Elaboration
  • Components and Configurations
    • Components
    • Configuring components instances
    • Direct instantiation
    • Basic configurations
    • Configuration declaration
    • Default binding
    • Configuration specification
  • Port map and Generic map
    • Genericity and automatic configuration of re-usable modules
  • Packages
    • Package Declarations
    • Package Bodies
    • Using package
  • Libraries
Exercise:  Designing a generic 4-digits BCD-counter and displaying it on a 7-segment display
Exercise:  Enhancing a 4-bit BCD-counter/decounter to create a generic one
Exercise:  Working with configurations
Exercise:  Designing a n digits BCD-counter/decounter and displaying it on a 7-segment display
Third Session
Design Methodology for Synthesis
  • Designing for Synthesis
  • Metastability
  • Memory Synthesis
  • Reset Generation
  • Crossing Clock domains
Exercise:  Metastability
Timing analysis and constraints
  • Timing Closure challenges
  • A methodology for successful Timing Closure
  • Common Timing Closure Issues
  • Static Timing Analysis
  • Role of Timing Constraints in STA
  • Common Issues in STA
  • Delay Calculation versus STA
  • Timing Path
  • Setup and Hold
  • Slack
  • On-Chip Variation
  • Clock
  • Port Delays
  • Completing Port Constraints
  • False Paths
  • Multi Cycle Paths
  • Combinational Paths
  • Xilinx Extensions
Exercise:  Design closure
Exercise:  Analyzing and Resolving timing violations
Fourth Session
Introduction to Open Source VHDL Verification Methodology (OSVVM)
  • Overview
  • Transaction-Level Modeling
  • Constrained Random Test Generation
  • Functional Coverage
  • Intelligent Coverage Randomization Methodology
  • Utilities for Testbench Process Synchronization
  • Transcript Files
  • Error Logging and Reporting – Alerts and Affirmations
Introduction to Universal VHDL Verification Methodology (UVVM)
  • Utility Library
  • VVC (VHDL Verification Component) Framework
  • BFMs (Bus Functional Models
  • OSVVM and UVVM
Vivado Debug
  • Vivado Integrated Logic Analyzer (ILA)
  • Adding debug nets
  • Analyzing debug data
  • Resources