Course dispensed using the Teams video-conferencing system.
The trainer answers trainees' questions during the training and provide technical and pedagogical assistance through the Teams video-conferencing system.
Practical activities
Practical activities represent from 40% to 50% of course duration.
Code examples, exercises and solutions
One Online Linux PC per trainee for the practical activities.
The trainer has access to trainees' Online PCs for technical and pedagogical assistance.
Eclipse environment and GCC compiler.
QEMU Emulated board or physical board connected to the online PC (depending on the course).
Some Labs may be completed between sessions and are checked by the trainer on the next session.
Downloadable preconfigured virtual machine for post-course practical activities
At the start of each session the trainer will interact with the trainees to ensure the course fits their expectations and correct if needed
Total: 18 hours
3 sessions, 6 hours each (excluding break time)
From 40% to 50% of training time is devoted to practical activities
Some Labs may be completed between sessions and are checked by the trainer on the next session
Any embedded systems engineer or technician with the above prerequisites.
The prerequisites indicated above are assessed before the training by the technical supervision of the traineein his company, or by the trainee himself in the exceptional case of an individual trainee.
Trainee progress is assessed in two different ways, depending on the course:
For courses lending themselves to practical exercises, the results of the exercises are checked by the trainer while, if necessary, helping trainees to carry them out by providing additional details.
Quizzes are offered at the end of sections that do not include practical exercises to verifythat the trainees have assimilated the points presented
At the end of the training, each trainee receives a certificate attesting that they have successfully completed the course.
In the event of a problem, discovered during the course, due to a lack of prerequisites by the trainee a different or additional training is offered to them, generally to reinforce their prerequisites,in agreement with their company manager if applicable.
Course Outline
The Finite State Machine Approach
Sequential Circuits and State Machines
State Transition Diagram
Transition Types
Moore-to-Mealy Conversion
Mealy-to-Moore Conversion
Exercises
Hardware Fundamentals
Flip-Flops
Metastability and Synchronizers
Pulse Detection
Glitches
Pipelined Implementations
Exercises
Hardware Architectures for State Machines
Fundamental Design Technique for Moore Machines
Fundamental Design Technique for Mealy Machines
Moore versus Mealy Time Behavior
State Machine Categories and State-Encoding Options
Safe State Machines
Design Steps and Classical Mistakes
Classical Problems and Mistakes
Design Steps Summary
Regular State Machines
Architectures for Regular Machines
Number of Flip-Flops
Exercises
Timed State Machines
Architectures for Timed Machines
Timer interpretation
Transition Types and Timer Usage
Timer Control Strategies
Time Behavior of Timed Moore and Mealy Machines
Examples of Timed Machines
Exercise:
Designing a burstable RAM controller
Designing for Synthesis
Metastability
Memory Synthesis
Reset Generation
Crossing Clock domains
Exercise:
Metastability
Timing Closure challenges
A methodology for successful Timing Closure
Common Timing Closure Issues
Static Timing Analysis
Role of Timing Constraints in STA
Common Issues in STA
Delay Calculation versus STA
Timing Path
Setup and Hold
Slack
On-Chip Variation
Clock
Port Delays
Completing Port Constraints
False Paths
Multi Cycle Paths
Combinational Paths
Xilinx Extensions
Exercise:
Design closure
Exercise:
Analyzing and Resolving timing violations
Overview
Transaction-Level Modeling
Constrained Random Test Generation
Functional Coverage
Intelligent Coverage Randomization Methodology
Utilities for Testbench Process Synchronization
Transcript Files
Error Logging and Reporting – Alerts and Affirmations
Utility Library
VVC (VHDL Verification Component) Framework
BFMs (Bus Functional Models
OSVVM and UVVM
Vivado Integrated Logic Analyzer (ILA)
Adding debug nets
Analyzing debug data
Resources
To book a training session or for more information, please contact us on info@ac6-training.com.
Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.