TI3Cortex M4 Texas Instruments Implementation and Ti-RTOS
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Objectifs
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- Code Composer Studio (CCS) v9.0.1
- LAUNCHXL-CC1352P1(CC1352P microcontroller) Texas Instruments board
- Any embedded systems engineer or technician with the above prerequisites.
- The prerequisites indicated above are assessed before the training by the technical supervision of the traineein his company, or by the trainee himself in the exceptional case of an individual trainee.
- Trainee progress is assessed in two different ways, depending on the course:
- For courses lending themselves to practical exercises, the results of the exercises are checked by the trainer while, if necessary, helping trainees to carry them out by providing additional details.
- Quizzes are offered at the end of sections that do not include practical exercises to verifythat the trainees have assimilated the points presented
- At the end of the training, each trainee receives a certificate attesting that they have successfully completed the course.
- In the event of a problem, discovered during the course, due to a lack of prerequisites by the trainee a different or additional training is offered to them, generally to reinforce their prerequisites,in agreement with their company manager if applicable.
Course Outline
- Basic Knowledge on C language and microcontrollers
- ARM Cortex-M4 processor macrocell
- Programmer’s model
- Instruction pipeline
- Fixed memory map
- Privilege, modes and stacks
- Memory Protection Unit
- Interrupt handling
- Nested Vectored Interrupt Controller [NVIC]
- Power management
- Debug
- Special purpose registers
- Datapath and pipeline
- Write buffer
- System timer
- State, privilege and stacks
- System control block
- EXCEPTIONS
- Non-maskable exceptions
- Privilege, modes and stacks
- Fault escalation
- Priority boosting
- Vector table
- Basic interrupt operation, micro-coded interrupt mechanism
- Interrupt entry / exit, timing diagrams
- Interrupt stack
- Tail chaining
- Interrupt response, pre-emption
- Interrupt prioritization
- Interrupt handlers
| Exercise: | Interruption Management on Cortex-M4 | |
- Tasks and task descriptors
- Content of the task descriptor
- Lists of task descriptors
- Context switch
- Task scheduling and preemption
- Tick based or tickless scheduling
- Scheduling systems and schedulability proofs
- Fixed priority scheduling
- RMA and EDF scheduling
- Adaptive scheduling
- Synchronization primitives
- Waiting and waking up tasks
- Semaphores
- Mutual exclusion
- The priority inversion problem
- Priority inheritance (the automagic answer)
- Priority ceiling (the design centric answer)
- Mutexes and condition variables
- Mailboxes
- What is TI-RTOS ?
- Overview of TI-RTOS Components
- SYS/BIOS: The TI-RTOS Kernel
- TI-RTOS Networking and Networking Services
- TI-RTOS Drivers
- SYS/BIOS Packages
- SYS/BIOS and XDC Tools
- TI-RTOS Startup Sequence
- Configuring SYS/BIOS Using XDCTools
- Overview of Threading Modules
- Thread Characteristics
- Choosing the right Thread
- Thread Priorities preemption and yielding
- Introduction to Hooks
- Memory Map
- Placing sections into Memory Segments
- Stacks
- Cache configuration
- Dynamic Memory Allocation
- Heap implementations
- Introduction to Hwis
- Creating Hwi Objects
- Hwi APIs
- Hwi Interrupt Nesting and System Stack Size
- Hwi Hooks
| Exercise: | Configuring Hwis | |
| Exercise: | Configuring Hwis dynamically | |
- Introduction to Swis
- Creating Swi objects
- SWI interrupts nesting
- Using Swi bbject trigger variables
| Exercise: | Configuring Swis | |
| Exercise: | Configuring Swis dynamically | |
- Introduction to Task Threads
- Creating Tasks
- Task Execution states and scheduling
- Task Stacks
- Testing for stack overflow
- Task Hooks
- Task Yielding for time-slice scheduling
- Idle Loop
| Exercise: | Hwi, Swi, Task and Idle Threads | |
- Semaphores
- Event Module
- Gates
- Mailboxes
- Queues
| Exercise: | Synchronization Primitives (Semaphore, Gates and Events) | |
| Exercise: | Reader / Writers (Mailboxes) | |
- Clock
- Timer Module
- Seconds Module
- Timestamp
| Exercise: | Clock and Timer Threads | |
- Introduction
- Load Module
- Error Handling
- Instrumentation Tools in Code Composer studio
- Performance optimization
| Exercise: | Threads statistics (Hwis Global, Swi Global and Tasks) | |
- Timing Benchmarks
- Interrupt Latency
- Hwi-Hardware Interrupt
- Swi-Software Interrupt Benchmarks
- Task Benchmarks
- Semaphore Benchmarks
More
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Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 1 week before the course start.
Last update of course schedule: 23 February 2026
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