Communication

Adding a TCP/IP stack to an embedded system is rarely a matter of dropping in a library. The stack has to fit in the memory left after the application, run without starving the real-time tasks, and stay reliable when the link degrades.

Our course covers LwIP, the lightweight stack used across microcontroller projects: buffer and memory management, the network interface layer, the RAW, Netconn and socket APIs, driver integration on STM32, and the configuration choices that decide how much RAM the stack consumes.

The tuning is where LwIP is won or lost: the number and size of pbufs, the TCP window against available RAM, whether checksums are offloaded to the MAC, and how the driver hands buffers back. Get those wrong and the stack works on the bench then stalls under load. The course covers each of them on an STM32 target.

Every embedded system talks to something: a sensor over I2C, a host over USB, a backplane over PCI Express. Each bus carries its own electrical constraints, protocol layers and debug methods, and picking the wrong one shows up late in a design.

Our courses cover the buses in real use: CAN and MIL-STD 1553B for embedded control, USB 2.0 and 3.0, PCI and PCI Express, HDMI, and the digital interconnect standards that replaced shared buses. Each one is taught from the signal up to the software stack.

Each bus fails in its own way, and that is where the training time goes: arbitration and error frames on CAN, LTSSM link training and TLP ordering on PCI Express, enumeration and descriptor errors on USB, TMDS signal integrity on HDMI. The courses work at that level, with protocol analyzers on real traffic.

Networking in embedded systems is not general-purpose networking. Frames have deadlines, clocks have to stay aligned across nodes, and a stack has to fit in the memory left over once the application is loaded.

Our courses cover Ethernet and switching, 10 Gigabit Ethernet, and the IEEE1588 precise time protocol used where nodes must share a common clock. Implementation on real hardware, including the NXP and STM32 controllers, is part of every session.

The work sits in the details: descriptor rings and DMA between the MAC and memory, checksum and VLAN offload, PHY negotiation and link loss, and the hardware timestamping IEEE1588 needs to reach sub-microsecond accuracy. The courses cover these on the NXP eTSEC and STM32 controllers, with capture on real traffic.

Storage in an embedded product has to survive power loss, wear and years of field use. The interface choice drives throughput, latency and cost, and it is usually fixed early in the hardware design.

Our courses cover the standards in current use: Serial ATA III, SD UHS-II and Universal Flash Storage. Each is taught from the physical layer through the command set, with the host controller behavior you need to write or debug a driver.

Below the interface sits the flash itself: wear leveling, write amplification, and the difference between what a datasheet claims and what a device sustains once its blocks are aged. The courses cover the command sets, the host controller interfaces and the power-loss behavior that decides whether data survives.