Knowledge of ARM7/9 or having attended our course ARM fundamentals.
This course does not include chapters on low level programming.
ACSYS offers a large set of tutorials to become familiar with RVDS, assembly level programming, compiler hints and tips.
More than 12 correct answers to our Cortex-A5 prerequisites questionnaire.
PDF course material (in English) supplemented by a printed version for face-to-face courses.
Online courses are dispensed using the Teams video-conferencing system.
The trainer answers trainees' questions during the training and provide technical and pedagogical assistance.
At the start of each session the trainer will interact with the trainees to ensure the course fits their expectations and correct if needed
Any embedded systems engineer or technician with the above prerequisites.
The prerequisites indicated above are assessed before the training by the technical supervision of the traineein his company, or by the trainee himself in the exceptional case of an individual trainee.
Trainee progress is assessed by quizzes offered at the end of various sections to verify that the trainees have assimilated the points presented
At the end of the training, each trainee receives a certificate attesting that they have successfully completed the course.
In the event of a problem, discovered during the course, due to a lack of prerequisites by the trainee a different or additional training is offered to them, generally to reinforce their prerequisites,in agreement with their company manager if applicable.
INTRODUCTION TO CORTEX-A5
Cortex-A5 variants: single core vs multicore
The 4 instruction sets
States and modes
In-order pipeline operation
Branch prediction mechanism
TrustZone conceptual view
Secure to non secure permitted transitions
INTRODUCTION TO MULTI-CORE SYSTEMS
AMP vs SMP
Exclusive access monitor
Basic concepts of RTOS supporting A5 SMP architecture
THUMB-2 INSTRUCTION SET (V7-A)
General points on syntax
Branch and control flow instructions
Memory access instructions
Exception generating instructions
If…then conditional blocks
Stack in operation
Interworking ARM and Thumb states
Demonstration of assembly sequences aimed to understand this new instruction set
MEMORY MANAGEMENT UNIT
Page access permission, domain and page protection
Utilization of memory barrier instructions
Format of the external page descriptor table
Utilization of microTLBs
Abort exception, on-demand page mechanism
MMU maintenance operations
Maintaining coherency of multiple TLBs
LEVEL 1 MEMORY SYSTEM
Supported maintenance operations
Memory hint instructions
Describing transient cache related transactions: line fills and line eviction
64-bit merging store buffer
PMU related events
Snoop Control Unit: cache-to-cache transfers
MOESI state machine
Understanding through sequences how data coherency is maintained between L2 memory and L1 caches
Accelerator Coherency Port
Enabling coherency mode
PL301 AXI interconnect
AXI channels, channel handshake
Support for unaligned data transfers
Transaction ordering, out of order transaction completion
Cortex-A5 external memory interface, ID encoding
Power control, dynamic power management
Wait For Interrupt architecture
Level 2 memory interface
Exclusive L2 cache
PL310 LEVEL 2 CACHE
Understanding through sequences how cacheable information is copied from memory to level 1 and level 2 caches
Transient operations, utilization of line buffers LFBs, LRBs, EBs and STBs
Cache event monitoring
Describing each maintenance operation
Debugging a multi-core system with the assistance of the PMU
Cortex-A5 exception management
Integrated timer and watchdog unit in MPCore
Interrupt groups: SGI, PPI, SPI, LSPI
Prioritization of the interrupt sources
Distribution of the interrupts to the Cortex-A5 cores
Generation of interrupts by software
Detailing the interrupt sequence, purpose of Interrupt Acknowledge register and End-Of-Interrupt register
LOW POWER MODES
Communication to the power management controller
Standby and wait for event signals
SCU power status register
CORESIGHT DEBUG UNITS
Benefits of CoreSight
Invasive debug, non-invasive debug, taking into account the secure attribute
Connection to the Debug Access Port
Debug facilities offered by Cortex-A5
Debug Communication Channel
Cross-Trigger Interface, debugging a multi-core SoC
2370 € HT
This course can be provided either remotely, in our Paris training center or, worldwide, on your premises.
Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 2 working days before the course start (1 week for face-to-face courses).