First day
INTRODUCTION TO CORTEX-A5
- Cortex-A5 variants: single core vs multicore
- The 4 instruction sets
- Configurable options
ARM BASICS
- States and modes
- Exception mechanism
- Instruction sets
INSTRUCTION PIPELINE
- In-order pipeline operation
- Branch prediction mechanism
- Return stack
TRUSTZONE
- TrustZone conceptual view
- Secure to non secure permitted transitions
- Memory partitioning
- Interrupt management
- Boot sequence
INTRODUCTION TO MULTI-CORE SYSTEMS
- AMP vs SMP
- Boot sequence
- Exclusive access monitor
- Global monitor
- Spin-lock implementation
- Using events
- Basic concepts of RTOS supporting A5 SMP architecture
Second day
THUMB-2 INSTRUCTION SET (V7-A)
- General points on syntax
- Branch and control flow instructions
- Memory access instructions
- Exception generating instructions
- If…then conditional blocks
- Stack in operation
- Interworking ARM and Thumb states
- Demonstration of assembly sequences aimed to understand this new instruction set
MEMORY MANAGEMENT UNIT
- MMU objectives
- Address translation
- Page access permission, domain and page protection
- Utilization of memory barrier instructions
- Format of the external page descriptor table
- Tablewalk
- TLB organization
- Utilization of microTLBs
- Abort exception, on-demand page mechanism
- MMU maintenance operations
- Maintaining coherency of multiple TLBs
LEVEL 1 MEMORY SYSTEM
- Cache organization
- Supported maintenance operations
- Memory hint instructions
- Describing transient cache related transactions: line fills and line eviction
- 64-bit merging store buffer
- PMU related events
HARDWARE COHERENCY
- Snooping basics
- Snoop Control Unit: cache-to-cache transfers
- MOESI state machine
- Address filtering
- Understanding through sequences how data coherency is maintained between L2 memory and L1 caches
- Accelerator Coherency Port
- Enabling coherency mode
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