This course covers both Cortex-A9 single and multiple core high-end ARM CPUs
Objectives
This course is split into 3 important parts:
Cortex-A9(MP) architecture
Cortex-A9(MP) software implementation and debug
Cortex-A9(MP) hardware implementation
MMU operation under Linux is described.
Spin-lock implementation in a multicore system is also detailed
Interaction between level 1 caches, level 2 cache and main memory is studied through sequences.
The exception mechanism is explained, indicating how virtualization enables the support of several operating systems.
An overview of the Coresight specification is provided prior to describing the debug related units.
The course also describes the hardware implementation and provides some guidelines to design a SoC based on Cortex-A9.
Cache coherency is detailed, including cache tag mirrors, the advantage of connecting DMA channels to ACP and the sequences that have to be used to modify a page descriptor.