First day
INTRODUCTION TO CORTEX-A9
- Cortex-A9 variants
- New memory-mapped registers in MPCore
- The 3 instruction sets
- Configurable options
ARM BASICS
- States and modes
- Benefit of register banking
- Exception mechanism
- Instruction sets
INSTRUCTION PIPELINE
- Superscalar pipeline operation
- Branch prediction mechanism
- Return stack
- Predicted and non-predicted instructions
TRUSTZONE
- Secure to non secure permitted transitions
- L1 and L2 secure state indicators, memory partitioning
- Interrupt management when there is a mix of secure and non-secure interrupt sources
- Boot sequence
INTRODUCTION TO MULTI-CORE SYSTEMS
- AMP vs SMP
- Boot sequence
- Exclusive access monitor
- Spin-lock implementation
- Using events
- Basic concepts of RTOS supporting A9 SMP architecture
Second day
THUMB-2 INSTRUCTION SET (V7-A)
- General points on syntax
- Branch and control flow instructions
- Memory access instructions
- Exception generating instructions
- If…then conditional blocks
- Interworking ARM and Thumb states
- Demonstration of assembly sequences aimed to understand this new instruction set
MEMORY MANAGEMENT UNIT
- Page access permission, domain and page protection
- Page attributes, memory types
- Utilization of memory barrier instructions
- Format of the external page descriptor table
- TLB lockdown
- Abort exception, on-demand page mechanism
- MMU maintenance operations
- Using a common page descriptor table in an SMP platform, maintaining coherency of multiple TLBs
LEVEL 1 MEMORY SYSTEM
- Virtual indexing, physical tagging for instruction cache
- Supported maintenance operations
- Write-back write allocate cache allocation
- Memory hint instructions PLD, PLI, PLDW, data prefetching
- Describing transient cache related transactions: line fills and line eviction
- 4-entry 64-bit merging store buffer
HARDWARE COHERENCY
- Snooping basics: CLEAN, CLEAN & INVALIDATE and INVALIDATE snoop requests
- Snoop Control Unit: cache-to-cache transfers
- MOESI state machine
- Understanding through sequences how data coherency is maintained between L2 memory and L1 caches
- Accelerator Coherency Port
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