This course aims to highlight the new features offered by the V8 architecture.
It has been developed for engineers developing low level software.
First, an overview of Cortex-A57 is provided, to highlight the differences between a Cortex-A15/Cortex-A7 hardware platform based on CCI-400 and a Cortex-A57/Cortex-A53 hardware platform based on CCN-504.
The new exception mechanism is described.
The enhancements regarding the LPAE are detailed.
New A64 assembler instructions are explained through practical examples.
The AAPCS64 is also covered.
The course also details the new debug ARM V8 features.
Cortex-A57 hardware implementation is explained, particularly the low power states.
Knowledge of ARM Architecture V7 is mandatory, particularly the LPAE.
PDF course material (in English) supplemented by a printed version for face-to-face courses.
Online courses are dispensed using the Teams video-conferencing system.
The trainer answers trainees' questions during the training and provide technical and pedagogical assistance.
At the start of each session the trainer will interact with the trainees to ensure the course fits their expectations and correct if needed
Any embedded systems engineer or technician with the above prerequisites.
The prerequisites indicated above are assessed before the training by the technical supervision of the traineein his company, or by the trainee himself in the exceptional case of an individual trainee.
Trainee progress is assessed by quizzes offered at the end of various sections to verify that the trainees have assimilated the points presented
At the end of the training, each trainee receives a certificate attesting that they have successfully completed the course.
In the event of a problem, discovered during the course, due to a lack of prerequisites by the trainee a different or additional training is offered to them, generally to reinforce their prerequisites,in agreement with their company manager if applicable.
Memory interface that implements either an ACE or CHI interface
Coherent interface, studying examples of hardware coherency within a Cluster and between Clusters
SoC architecture based on CCN-504 interconnect
Enhancement with regard to AArchv7
Register mapping between A32/T32 and A64
Mapping of AArch64 System registers to the AArch32 System registers
Security model when EL3 is using AArch64
Trapping to EL3 using AArch64
Managing two types of processes: 64-bit and 32-bit, switching on an exception
Non secure space organization
The effect of implementing EL2 on the Exception model
• Four exception levels
Exception Link Registers
Register banking by exception level based on a new exception model
Nesting on the same exception level
Exception type and exception origin
Syndrome registers used to provide a status information to the exception handler
Exception return instruction
Predicted and non-predicted instructions
BTB invalidation and context switches
Synchronization and semaphores
Shareability memory attributes
Operation of the global monitor
Load acquire / Store release instruction pair
Use of WFE and SEV instructions by spin-locks
Program counter and stack pointer alignment
Page attributes : Normal or Device
Shareability and access limitations on the data barrier operations
LPAE enhancements to adapt to AArch64
Supporting up to 48 bits of VA per TTBR
Access permission checking
Supporting up to 48 bits of IPA and PA spaces
VMSAv8-64 address translation system
Memory translation granule size
Descriptor page table organization, descriptor format
Hierarchical control of Secure or Non-secure memory accesses
TLB preload instructions
TLB maintenance instructions in A64
Cortex-A57 TLB implementation
Cache hierarchy, Point of Unification, Point of Coherency
Load non temporal instruction
Instruction and Data cache maintenance instructions in A64
Cortex-A57 L1 and L2 memory system
A64 assembly language, regular bit encoding structure