FIRST DAY
AXI3 PROTOCOL
- ARM AMBA versions
- Basic read and write transactions, pipelining, data reordering
- Global signals, clocking, low power handshake interface
- Detailing address channel signals
- Detailing data channel signals
- Detailing response signals
- Ordering model
- Managing exclusive resources
AXI4 NEW SIGNALS
- QoS signalling, defining a per-transaction priority
- Multiple region signalling
AXI4 LITE
- Simpler control register-style interface
- Bursts of 1 data beat
- Conversion, protection and detection
AXI4 STREAM
- Objectives of this new protocol
- Byte stream example
- Merging and packing
- Downsizing / upsizing
- Packet transfer
NIC-301 AXI3 INTERCONNECT
- TrustZone support
- Programmable features, QoS
- Arbitration algorithms
- Programmer’s model
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SECOND DAY
INTRODUCTION TO CACHE AND TLB COHERENCY
- Cache organization
- Explaining the need for coherency
- Translation Lookaside Buffer
- Implementing an I/O MMU
AXI COHERENCY EXTENSION
- Signals added to the traditional 5 channels
- Explaining what is a shareability domain
- Using barriers, related ARM instructions
- The three additional channels
- ACE new transactions: explaining through sequences their utilization
- Distributed virtual memory
- ACE-lite subset
CCI-400 AXI4 ACE INTERCONNECT
- SoC architecture example
- Implementation in a Big/little system
- Performance monitoring unit
- TrustZone support
- QoS value arbitration and propagation
- Regulation of outstanding transactions
- QoS value based on latency measurement
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