First day
ARM Cortex-M1 INTRODUCTION
- Programmer's model
- Fixed memory map
- Privilege, modes and stacks
- Memory Protection Unit
- Interrupt handling
- Nested Vectored Interrupt Controller [NVIC]
- Power management
- Debug
ARM Cortex-M1 CORE
- Datapath and pipeline
- Write buffer
- Bit-banding
- System timer
- State, privilege and stacks
- System control block
- Different level of debug implementation
EXCEPTIONS
- Exception behavior, exception return
- Non-maskable exceptions
- Privilege, modes and stacks
- Fault escalation
- Vector table
OVERVIEW OF THUMB-2 INSTRUCTION SET
- Data processing instructions
- Branch and control flow instructions
- Memory access instructions
- Exception generating instructions
- If...then conditional blocks
- Exclusive load and store instructions
- Accessing special registers
- Memory barriers and synchronization
Second day
INTERRUPTS
- Interrupt entry / exit, timing diagrams
- Tail chaining
- Interrupt response, pre-emption
- Interrupt prioritisation
- Interrupt implementation configurability, impact on core size
MEMORY TYPES
- Memory types, restriction regarding load / store multiple
- Device and normal memory ordering
- Access order
- Memory barriers
INVASIVE DEBUG
- Cortex-M1 debug features
- Monitor mode
- Flash patch and breakpoint features
- Data watchpoint and trace
- DWT registers
- AHB-Access Port
INTEGRATION
- Functional Integration
- Clocking
- Reset
- AHD and Debug interfaces
- Synthesis, Place and Route
- Sign-Off
Third day
IMPLEMENTATION
- Implementation flow
- Configuration options
- RTL Validation
- Synthesis
- Place and route
- Qualification
AMBA3.0 INTERCONNECT SPECIFICATION
- Purpose of this specification
- Example of SoC based on AMBA specification
- Differences between AMBA2.0 and AMBA3.0
AHB - ADVANCED HIGH PERFORMANCE BUS
- Centralized address decoding
- Address gating logic
- Arbitration, bus parking
- Single-data transactions
- Sequential transfers
- Retry response
- Split response
- AHB-lite specification
APB - ADVANCED PERIPHERAL BUS
- Read timing diagram
- Write timing diagram
- Operation of the AHB-to-APB bridge
- APB3.0 new features
AHB CORTEX-M1 PORTS
- Clocking and reset
- Bus interfaces , AMBA-3 compliance
- Debug interface, AHB-AP programming interface
- Connection to the TPIU
registration form
