OVERVIEW
- PCI specifications history
- PCI bus features
- PCI device types
- Technological introduction
- Architecture of recent PCs
PCI DEVICE ARCHITECTURE
- Information buffering
- Buffer management
- Prefetchable vs non-prefetchable memory ranges
- Synchronization rules
- Producer / consumer model
- Optional processings
- PCI bus limitations
TRANSFER PROTOCOL
- Transfer basics
- Pinout, signal classes
- Arbitration
- Data transfer protocol
- Address decoding in IO, MEM and CFG spaces
- 64-bit data transfer
- 64-bit addressing
- Master initiated terminations
- Target initiated terminations
- Fast back-to-back
- Parity control
- Shared resource management
- Bus analyse, benefit of a bus analyser / exerciser
INTERRUPTS AND RESET
- PCI interrupts
- Interrupt acknowledge transaction
- Interrupt sharing
- Message Signaled Interrupts
- MSI-X
- Reset, operating states
CACHE COHERENCY
- Cache basics
- Snooping basics
- Cacheability of RAM accessed by the host CPU through PCI
- PCI masters accessing the host memory
- PCI agent processor accessing the host memory
ELECTRICAL SPECIFICATION
- Switched wave switching vs Incident wave switching
- Static specification
- Dynamic specification : 33 MHz and 66 MHz
- Clocking
- Decoupling
- Routing and layout recommendations
- Compliance checklists
CONFIGURATION SPACE
- Configuration space mappings
- Register description
- PCI MEM and PCI IO mappings building
- Expansion ROM
- Capability list
- Configuration transactions, IDSEL routing
- Local vs distant CFG transaction
- Generation of config transactions
PCI-TO-PCI TRANSPARENT BRIDGES
- Bus numbering
- Address decode, transaction forwarding rules
- Distant configuration cycles
- Error management
POWER MANAGEMENT
- Bus power state machine
- PCI function power state machine
- Programming interface
PCI BASED INDUSTRIAL SPECIFICATIONS
- Passive bus PICMG PC
- CMC/PMC mezzanine boards, BUSMODE pins management
- CompactPCI introduction
- PC104+ introduction
- PC.MIP introduction
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