- This course aims to clarify the Cyclone-V Cortex-A9 Hard Processor System.
- The interconnect based on ARM NIC-301 is particularly detailed.
- Hardware implementation of the Cortex-A9 is described, including reset and clocking.
- The possible boot sequences, involving or not the FPGA configuration, are explained.
- Interaction between level 1 caches, level 2 cache and main memory is studied through sequences.
- MMU operation is described.
- Spin-lock implementation in a multicore system is also detailed.
- The exception mechanism is explained, focusing on Cyclone-V interrupt mapping.
- An overview of the Coresight specification is provided prior to describing the debug related units and general Cyclone-V debug infrastructure, involving both the Hard Processor System and the FPGA portion.
- The operation of the Snoop Control Unit when supporting SMP is fully explained, particularly the utilization of cache tag mirrors, the advantage of connecting DMA channels to ACP and the sequences that have to be used to modify a page descriptor.
- Integrated SDRAM and Flash controllers, which can be accessed by FPGA masters and processor block masters, are fully described.
- Integrated peripherals are studied, especially the gigabit Ethernet MACs and the USB2.0 OTG controllers.
- Products and services offered by ACSYS:
- AC6 is able to assist the customer by providing consultancies. Typical expertises are done during system architecture definition, software debugging, performance tuning.
- Note that AC6 has a long experience with processor implementation in civil avionics systems.
||Labs included in this course are compiled with RVDS 4.1 and executed under Lauterbach Trace32.
||A more detailed course description is available on request at email@example.com
||This document is necessary to tailor the course to specific customer needs and to define the exact schedule.