Starting with a simple "Hello Word" Project
- Tools Introduction :
- The Vivado Design Suite
- EDK
- Development flow introduction
- Hardware Development
- Software Development
- Verification (Simulation and Debug)
- Flashing with Impact
| Exercise: |
Creating the Hardware and Software to send strings on a serial port |
The MicroBlaze Logicore IP (MCS)
- Microcontroller system
- Features
- Overview
- Designing with the core
- Microblaze architecture overview
- Core block overview
- Introduction and configurable features
- Data type and Endianness
- Register Bank (General Purpose Registers and Special Registers)
- Pipeline
- Branches
- Privilege Modes
- Hardware Exception
- Breaks
- Interrupts
- Vector Table
- Floating Point Unit
- Caches and MMU Overview
- Debug
- MicroBlaze ABI
- MicroBlaze Interface Overview
- MicroBlaze I/O Overview
- AXI4 bus, AXI-Lite
- AXI-Stream
- PLB (Peripheral Local Bus)
- LMB (Local Memory Bus)
- FSL (Fast Simplex Link Interface)
- XCL (Xilinx CacheLink Interface)
- Debug Interface
- MicroBlaze Core Configurability
| Exercise: |
Looking at the MicroBlaze core configuration wizard |
| Exercise: |
Area size analysis on different systems (with/without caches, AXI/PLB) |
Hardware Design- Xilinx Platform Studio (XPS)
- Introduction
- Platgen
- Simgen
- Generating the Simulation Models and the Testbench
- Loading an application
- XPS Interface Description
- MHS, MPD, PAO files Description
- Accessing peripheral information (Datasheet, MPD, etc.)
- Bus and Periphral Connexion
- Peripheral definition files
- Platgen tool
| Exercise: |
Enhancing the "Hello World" Platform (Adding Interrupt Controller, Timer, GPIO, RAM) |
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Working with bus interfaces, Ports and Memory mapping |
| Exercise: |
Simulating the platform with ISim through ISE Project Navigator |
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Analysing the Instruction fetching on the Instruction AXI bus |
Software Design- The Software Development Kit (SDK)
- Introduction
- Libgen
- Scanned repositories for software component
- Startup
- Linker Script
- MSS, MLD, MDD files description
- Board Support Package Specification
- Using Xilinx IP Drivers
- Interrupt Management
- Block RAM initialization (Data2Mem)
- Debugging (Memory, Registers, Disassembly views, etc.)
- Generating the Linker Script (Placing Code and Data in different memories)
- Executing the application from an External DDR3 Memory (using a bootloader)
- Profiling
- Rebuilding the application and the BSP with the correct compiler flags to use profiling
| Exercise: |
Developing the software for the hardware platform created with XPS |
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Timer Implementation |
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Interrupt management |
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Creating a Blinky |
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Generating Interrupts from GPIOs |
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Placing the application code/data in different memories |
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Using Profiling |
Custom Peripheral Creation and Insertion
- Create or Import Peripheral (CIP) Wizard Introduction
- LogiCORE IP AXI Lite IPIF to connect a slave peripheral on the bus
- Creating HDL and MPD templates through XPS
- Directory Structure generated
- IP development and Simulation through ISE
- Developing a user IP and a testbench
- Understanding how to create software registers (memory mapped)
- Simulating the IP
- Importing a Custom IP to XPS
- Connecting a Slave IP on the AXI-Lite Bus
| Exercise: |
Developing and Simulating a custom IP (controlling LED intensity with a PWM) through ISE |
| Exercise: |
Using the CIP wizard to implement this user IP into our platform (SoC) |
| Exercise: |
Developing the software application to program the IP through SDK |
The ChipScope Hardware Debugger
- Introduction to Chipscope Pro
- Implementing an AXI monitor into the design to analyze AXI4-Lite Bus transactions
- Retrieving the on-chip signals waveforms using Chipscope Pro Analyzer
- Clarifying trigger conditions
| Exercise: |
Connecting a Chipscope Analyzer to the AXI bus on our custom IP side and, using it to measure bandwidths |
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