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ac6 >> ac6-training >> Programming >> Logique Programmable >> RISC-V CPU Download Catalog Download as PDF Write us Printable version


This course covers and explains the implementation of the RISC-V CPU on FPGA platforms

  • This course aims to highlight the the RISC-V architecture and the SiFive E31 core
  • It has been developed for engineers developing low level software
  • First, an Introduction of RISC-V ISA is provided, to highlight the differences between RISC-V modules
  • Although the E31 RISC-V seems to a simple 32-bit core, it supports sophisticated mechanisms, such as Physical Memory Protection, Global and external interrupt and debug units
  • The Microchip Polarfire Implementation and Embedded Development Kit (EDK) with Libero SoC PolarFire and software Integrated Development environment (IDE) tools are described to create a hardware platform and the software to execute to program it
  • The course also details the SiFive High performance TileLink Interface
  • A more detailed course description is available on request at training@ac6-training.com
A more detailed course description is available on request at training@ac6-training.com
Course environment
  • Microchip LiberoSoC PolarFire v2.2 and SoftConsole v5.2
  • AVMPF300TS (Microchip PolarFire-based) board
  • Basic knowledge on processor and FPGA technology
  • Knowledge of VHDL and C languages

First Day
Introduction to RISC-V ISA Modules
  • RV32-I/E and RV64-I/E Base Integer Instruction SET
  • Integer Multiplication and division
  • Atomic Instructions
  • Floating Point precision(Single-double-Quad)
  • Compressed Instructions
  • SIMD instructions
  • User-Level interrupts
Privileged Architecture
  • Control and Status Registers (CSRs)
  • Machine-Level ISA
  • Supervisor-Level ISA
  • RISC-V Interrupts
RISC-V Debug Support
  • System Overview
  • Debug Module
  • RISC-V Debug
  • Trigger Module
  • Debug Transport Module
SiFive E31 Core and Interfaces
  • Core Complex Interfaces
  • Memory Map
  • Interrupts
  • Platform-Level Interrupt Controller
  • Core Local Interrupter (CLINT)
  • Physical Memory Protection
Second Day
Libero SoC PolarFire
  • Microchip FPGA & SoC overview
  • Libero SoC PolarFire overview
  • Create and Design
  • Constraint management
  • TestBench and Simulations
  • Program and Debug
  • Microchip tools
Exercise:  Create a New Project
Exercise:  TestBench, Simulation
Exercise:  Synthesize the design
Exercise:  Place & Route
Third Day
Programming the RISC-V Core
  • SoftConsole
    • Overview and Firmware drivers
    • Supported platforms
    • Packages
    • Related Microchip Tools and resources
    • RISC-V Hardware Abstraction Layer (HAL)
  • SmartDebug
    • Introduction and SmartDebug User Interface
    • Debugging
    • RISC-V project
    • Debugging and Troubleshooting
Exercise:  Building a RISC-V Processor subsystem
Exercise:  Creating a RISC-V SoftConsole Project
Exercise:  Managing interrupts and priorities
Fourth Day
  • AXI architecture overview
    • Overview
    • Address Channels
    • Data Response Channels
    • Global and Low Power Interface Signals
  • AXI Interconnection Architectures
  • AXI vs AHB
AHB – Advanced High Performance Bus
  • Centralized address decoding
  • Address gating logic
  • Address pipelining
  • Sequential transfers
  • AHB-lite specification
APB – Advanced Peripheral Bus
  • Second-level address decoding
  • Operation of the AHB-to-APB bridge
  • APB3.0 new features
SiFive TileLink
  • Architecture
  • Signal descriptions
  • Serialization
  • Operations and Messages