First Day
From the logic gate to the CPLDs and FPGAs
- Reminder on digital electronic
- Structure of an Integrated Circuit
- SSI (small scale integration), TTL
- MSI (medium scale integration), PALs, GALs, PLDs
- LSI (large scale integration), CPLDs
- VLSI (very large scale integration), ASICs, ASSPs, FPGAs
- Logical architectures evolution
- The various components
- Technologies available on the market
- Technology constraints
- Interconnection methods (SRAM, Fuse, AntiFuse, Flash)
- Clock distribution
- Logic element types
- Timing issues
HDL Contribution
- Interest of HDL programming
- Different steps of the design
- Programming
- Simulation
- Synthesis
- Mapping
- Place and Route
- Timing Analysis
- Bitstream generation
- Definition of a project
- Structure of a program
- Allocation of PIN-OUT
- Programming
Exercise: |
Understanding the steps of design and programming: |
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Getting started with the ISE IDE |
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Creating a project from scratch |
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Synthesis, Translate |
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Map |
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Place and Route (PAR) |
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BitGen |
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Report Analysis |
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Assigning I/O locations using Planahead (editing constraint file) |
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Schematics |
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Analyzing the placement |
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Flashing with Impact |
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Second Day
Schematic Editor
- The schematic capture
- Primitives and symbols definition
- Resources definition
- Compilation
Exercise: |
Developing a new IP with the Schematic Editor, Designing a Bound Detector |
HDL Basic Concepts (VHDL and Verilog)
- Entity/ Architecture and Module
- Signals and wires
- Processes and Always/Initial statements
- Connecting existing IPs together
Exercise: |
Adding a 7-Segment Display to your design |
Test benches and simulation
- HDL instructions specific to simulation
- Functional and behavioral simulation (with delays)
- Test vector generation
Exercise: |
Getting started with the ISIM simulator, developing a tesbench and simulating the previous designs |
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