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ac6 >> ac6-training >> Processors >> NXP ARM SoCs >> i.MX6 Implementation Download as PDF Write us

FA4 i.MX6 Implementation

This course describes the i.MX6 Dual and Quad core SoC

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OBJECTIVES
  • The course details the hardware implementation of the i.MX6 SoC.
  • The course focuses on the boot sequence, the clocking and the power management strategies.
  • The course explains all parameters that affect the performance of the system in order to easily perform the final tuning.
  • The multiple complex units involved in multimedia management are covered in depth.
  • An overview of the Cortex-A9MP core helps to understand issues caused by MMU, cache and snooping.
  • Interrupt management through ARM GIC is explained through a lab.
  • The course also covers the hardware implementation, particularly the DDR3 and NAND flash controllers.

  • Note that these course outlines cover all units within the i.MX6
    • According to the actual reference chosen by the customer, some chapters may be removed.

  • Products and services offered by ACSYS:
    • ACSYS is able to assist the customer by providing consultancies. Typical expertises are done during board bringup, hardware schematics review, software debugging, performance tuning.
This course is only provided on-demand; A more detailed course description is available on request at training@ac6-training.com
This document is necessary to tailor the course to the specific customer needs and to define the exact schedule.
  • Theoretical course
    • PDF course material (in English) supplemented by a printed version for face-to-face courses.
    • Online courses are dispensed using the Teams video-conferencing system.
    • The trainer answers trainees' questions during the training and provide technical and pedagogical assistance.
  • At the start of each session the trainer will interact with the trainees to ensure the course fits their expectations and correct if needed
  • Any embedded systems engineer or technician with the above prerequisites.
  • The prerequisites indicated above are assessed before the training by the technical supervision of the traineein his company, or by the trainee himself in the exceptional case of an individual trainee.
  • Trainee progress is assessed by quizzes offered at the end of various sections to verify that the trainees have assimilated the points presented
  • At the end of the training, each trainee receives a certificate attesting that they have successfully completed the course.
    • In the event of a problem, discovered during the course, due to a lack of prerequisites by the trainee a different or additional training is offered to them, generally to reinforce their prerequisites,in agreement with their company manager if applicable.

Course Outline

  • ARM core based architecture
  • On-chip memories
  • Clarifying the internal data paths: AXI interconnect, AHB bus, peripheral buses
  • Organization of a board based on i.MX6
  • Memory mapping
  • IOMUX module, understanding how to select the function supported by each pin
  • Pad settings
  • General Purpose Input interrupt request capability
  • Instruction sets
  • Pipeline description
  • MMU and TLBs
  • Level 1 caches
  • Cache coherency
  • Cortex-A9MP and PL310 L2 cache IP instantiation options
  • Integrated interrupt controller (GIC), detail of interrupt mapping
  • AHB to IP Bridge
  • AHB-to-APBH Bridge with DMA
  • NIC-301 AXI interconnect
  • Power supplies
  • Clock Control Module
  • System Reset Controller
  • General Power Controller
  • Introduction to CoreSight, DAP features
  • System Secure Controller SJC
  • Embedded Trace Macrocell
  • Cross Triggering Interfaces
  • ARM TrustZone architecture
  • Cryptographic Acceleration and Assurance Module
  • Secure Non Volatile Storage
  • Run-Time Integrity Checker
  • Central Security Unit
  • Advanced High Assurance boot
  • Overview, basic script routines
  • Mapping DMA requests to channels
  • Channel priority definition
  • Scheduler
  • Instruction description
  • PCU states
  • Context switching
  • Multi-Mode DDR Controller
  • General-Purpose Media Interface
  • EIM unit
  • S-ATA II
  • Ultra SDHC
  • A simple processing flow of Multimedia application
  • Video Processing Unit
  • Image Processing Unit v3
  • Graphics Processing Unit 2D
  • Graphics Processing Unit 3D
  • Overview of audio subsystem
  • SSI interfaces
  • Digital audio multiplexor
  • SPDIF transmitter
  • Enhanced Serial Audio Interface (ESAI)
  • Asynchronous Sample Rate Converter
  • PWM
  • Gen 2 operation
  • 1-lane
  • Configuration as Agent or Root Complex
  • Interrupt management
  • PHY parameterizing
  • HSI
  • Enhanced CSPI
  • I2C interfaces
  • UART
  • USB
  • Gigabit Ethernet Controller
  • MediaLB
  • FlexCAN controllers