FA4i.MX6 Implementation
This course describes the i.MX6 Dual and Quad core SoC
OBJECTIVES
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- This course provides only an overview of the Cortex-A9MP
- Our course reference R1 - ARM7/9 implementation course details the operation of this complex ARM CPU.
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Our course reference RC1 - NEON-v7 programming course explains how to vectorize and implement algorithms to be executed by NEON SIMD engine.
- The following courses could be of interest:
- USB Full Speed High Speed and USB On-The-Go, reference IP2 - USB 2.0 course
- Ethernet and switching, reference N1 - Ethernet and switching course
- IEEE1588, reference N2 - IEEE1588 - Precise Time Protocol course
- CAN bus, reference IA1 - CAN bus course
- Memory cards, reference IS2 - eMMC 5.0 course
- SATA, reference IS3 - Serial ATA III course
- PCI Express, reference IC4 - PCI Express 3.0 course
- Theoretical course
- PDF course material (in English) supplemented by a printed version for face-to-face courses.
- Online courses are dispensed using the Teams video-conferencing system.
- The trainer answers trainees' questions during the training and provide technical and pedagogical assistance.
- At the start of each session the trainer will interact with the trainees to ensure the course fits their expectations and correct if needed
- Any embedded systems engineer or technician with the above prerequisites.
- The prerequisites indicated above are assessed before the training by the technical supervision of the traineein his company, or by the trainee himself in the exceptional case of an individual trainee.
- Trainee progress is assessed by quizzes offered at the end of various sections to verify that the trainees have assimilated the points presented
- At the end of the training, each trainee receives a certificate attesting that they have successfully completed the course.
- In the event of a problem, discovered during the course, due to a lack of prerequisites by the trainee a different or additional training is offered to them, generally to reinforce their prerequisites,in agreement with their company manager if applicable.
Course Outline
- ARM core based architecture
- On-chip memories
- Clarifying the internal data paths: AXI interconnect, AHB bus, peripheral buses
- Organization of a board based on i.MX6
- Memory mapping
- IOMUX module, understanding how to select the function supported by each pin
- Pad settings
- General Purpose Input interrupt request capability
- Instruction sets
- Pipeline description
- MMU and TLBs
- Level 1 caches
- Cache coherency
- Cortex-A9MP and PL310 L2 cache IP instantiation options
- Integrated interrupt controller (GIC), detail of interrupt mapping
- AHB to IP Bridge
- AHB-to-APBH Bridge with DMA
- NIC-301 AXI interconnect
- Power supplies
- Clock Control Module
- System Reset Controller
- General Power Controller
- Introduction to CoreSight, DAP features
- System Secure Controller SJC
- Embedded Trace Macrocell
- Cross Triggering Interfaces
- ARM TrustZone architecture
- Cryptographic Acceleration and Assurance Module
- Secure Non Volatile Storage
- Run-Time Integrity Checker
- Central Security Unit
- Advanced High Assurance boot
- Overview, basic script routines
- Mapping DMA requests to channels
- Channel priority definition
- Scheduler
- Instruction description
- PCU states
- Context switching
- Multi-Mode DDR Controller
- General-Purpose Media Interface
- EIM unit
- S-ATA II
- Ultra SDHC
- A simple processing flow of Multimedia application
- Video Processing Unit
- Image Processing Unit v3
- Graphics Processing Unit 2D
- Graphics Processing Unit 3D
- Overview of audio subsystem
- SSI interfaces
- Digital audio multiplexor
- SPDIF transmitter
- Enhanced Serial Audio Interface (ESAI)
- Asynchronous Sample Rate Converter
- PWM
- Gen 2 operation
- 1-lane
- Configuration as Agent or Root Complex
- Interrupt management
- PHY parameterizing
- HSI
- Enhanced CSPI
- I2C interfaces
- UART
- USB
- Gigabit Ethernet Controller
- MediaLB
- FlexCAN controllers
More
To book a training session or for more information, please contact us on info@ac6-training.com.
Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.
You can also fill and send us the registration form
This course can be provided either remotely, in our Paris training center or worldwide on your premises.
Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 1 week before the course start.
Last update of course schedule: 18 October 2022
Booking one of our trainings is subject to our General Terms of Sales