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ac6 >> ac6-training >> Processors >> NXP Power CPUs >> e200z7 implementation

FCC3 e200z7 implementation

This course covers the e200z7 core present in NXP MPC56XX MCUs

Objectives

This course has 5 main objectives:

Learning the exception mechanism, providing guidelines to implement nesting
Explaining the operation and initialization of the MMU and caches
Highlighting the cache coherency issues and explaining the snooping
Detailing low level programming, particularly the floating-point and SPE instructions
Describing the debug units.

ACSYS has developed an optimized SPE based FFT coded in assembler language.
For any information contact training@ac6-training.com

A more detailed course description is available on request at training@ac6-training.com

Prerequisites

Experience of a 32-bit processor or DSP is mandatory.

CORE ARCHITECTURE

e200 core family
Main blocks, pipeline, MMU, cache, timers, debug unit

INSTRUCTION PIPELINE

Prefetch queue
Decode / dispatch stage
Concurrent Instruction Issue Capabilities
In order execution
Completion, register write-back
Dynamic vs static branch prediction
Guarded memory

SUPERVISOR PROGRAMMING, EXCEPTION MECHANISM

Building the exception vector table
Exception taking sequence
Implementing nesting among maskable interrupts
Reset sequence

INSTRUCTION AND DATA PATH

Studying cache reload transients
Line-fill buffers
Memory synchronization
Spin-lock routine

MEMORY MANAGEMENT UNIT

Assigning attributes to pages
Assigning access permissions to page
Page protection
MMU-related exceptions
64-entry, fully associative TLB
TLB software reload, using MAS registers

LEVEL ONE CACHES

4 way set-associative Harvard instruction and data caches
Data and instruction prefetch instructions
Cache software control, cache line lock
Coherency issues when cacheable pages are shared with DMA
Cache parity and EDC protection
Cache memory access via software

PARALLEL SIGNATURE UNIT

System integrity checking
Monitoring the internal CPU read and write buses

USER-LEVEL PROGRAMMING

EABI, small sections
Tricky instructions
C coding guidelines

SIGNAL PROCESSING ENGINE

Half-precision floating-point format
Floating point simple precision & double precision scalar instructions
Floating point vector instructions
Fixed point vector instructions, fractional format
Vector data arrangement instructions
Managing a circular buffer

VARIABLE LENGTH ENCODING

VLE storage addressing
MMU extensions
Summary of instruction set

CORE TIMERS

64-bit time base
Decrementer
Software watchdog

DEBUG

Performance monitor
Nexus Class 3+ real-time development unit
Hardware instruction and data breakpoints
Debug interrupt
Debug notify halt instruction
Using debug data acquisition message
Watchpoint programming
Instruction and data trace

POWER MANAGEMENT

Power-saving modes: doze, nap, sleep, and wait
Debug considerations for power management

This course can be provided either remotely or in our Paris training center or, worldwide, on your premises.

Scheduled classes are confirmed as soon as there is two confirmed bookings.

To book a training session or for more information, please contact us on info@ac6-training.com.

Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.

You can also fill and send us the registration form

Last update of course schedule: 15 November 2021

Booking one of our trainings is subject to our General Terms of Sales

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