CORE ARCHITECTURE
- e200 core family
- Main blocks, pipeline, MMU, cache, timers, debug unit
INSTRUCTION PIPELINE
- Prefetch queue
- Decode / dispatch stage
- Concurrent Instruction Issue Capabilities
- In order execution
- Completion, register write-back
- Dynamic vs static branch prediction
- Guarded memory
SUPERVISOR PROGRAMMING, EXCEPTION MECHANISM
- Building the exception vector table
- Exception taking sequence
- Implementing nesting among maskable interrupts
- Reset sequence
INSTRUCTION AND DATA PATH
- Studying cache reload transients
- Line-fill buffers
- Memory synchronization
- Spin-lock routine
MEMORY MANAGEMENT UNIT
- Assigning attributes to pages
- Assigning access permissions to page
- Page protection
- MMU-related exceptions
- 64-entry, fully associative TLB
- TLB software reload, using MAS registers
LEVEL ONE CACHES
- 4 way set-associative Harvard instruction and data caches
- Data and instruction prefetch instructions
- Cache software control, cache line lock
- Coherency issues when cacheable pages are shared with DMA
- Cache parity and EDC protection
- Cache memory access via software
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