- This course has 6 main objectives:
- Describing the hardware implementation, particularly the boot sequence and the DDR3 controller
- Understanding the features of the internal interconnect and related units and mechanisms such as PAMU, CPC and stashing
- Describing the units which are interconnected to other modules, such as clocking, interrupt controller and DMA controller, because the boot program generally has to modify the setting of these units
- Explaining the standard bus interface controllers, PCIe, SRIO, USB, SATA and MMC-SD
- Clarifying the operation of the Datapath Acceleration Architecture that assists the processor core in taking in charge buffer allocation, queue management, frame management and particularly incoming frame classification, pattern searching, and encryption
- Describing the various debug units and their utilization to fix errors in a multicore / multimaster SoC.
- Products and services offered by ACSYS:
- ACSYS is able to assist the customer by providing consultancies
- Typical expertises are done during board bringup, hardware schematics review, software debugging, performance tuning.
- Note that ACSYS has delivered several consultancies on NXP Netcomm SoCs to companies developing avionic equipments.
|A more detailed course description is available on request at email@example.com
|This document is necessary to tailor the course to specific customer needs and to define the exact schedule.