P3041 ARCHITECTURE
SOC ARCHITECTURE
- Internal architecture
- CoreNet coherency fabric
- Coherency subdomains
- Memory map, local access windows
- Multicore processing scenarios
SOC PLATFORM
POWER, RESET AND CLOCKING
- Power management control
- Configuration signals sampled at reset
- Reset configuration words source
- Pre-boot loader
- Clocking, system clock domains
- Dynamically changing core clocks
- SerDes high speed lanes configuration
SECURE BOOT
- Objectives of trust architecture
- Secure boot sequence
- External tamper detection
- Run time integrity checker
CORENET PLATFORM CACHE
- Operation as memory-mapped SRAM
- Partitioning between coherency domains
- Stashing
- Soft error detection and correction
PERIPHERAL ACCESS MANAGEMENT UNIT (PAMU)
- Controlling master access permissions through Logical I/O Device Number
- Address translation
- Descriptor organization
- Operation mode translation
- Steps in processing of DSA operations by pamu
- PAMU caches
MULTIPROCESSOR PERIPHERAL INTERRUPT CONTROLLER
- Interrupt nesting
- Description of the 4 timers / counters
- Message interrupts
- e500-to-e500 interrupt capability
LOW SPEED PERIPHERALS
- UART
- I2C controller
- eSPI controller
ENHANCED SDHC
- Transfer protocol, single block, multiple block read and write
- Internal and external DMA capabilities
- SD protocol unit
- Card insertion and removal detection
USB CONTROLLERS
- Host or device support
- EHCI support, scheduling the various transactions into frames
- Integrated PHY
- Endpoint configuration
- Non-EHCI tuning control registers
HARDWARE IMPLEMENTATION
THE DDR3 / 3L MEMORY CONTROLLER
- DDR3 fly-by architecture, write leveling
- ZQ calibration
- Command truth table
- Hardware interface
- Initial configuration following Power-on-Reset
- Controller interleaving support
- Address decode unit
- Timing parameters programming
ENHANCED LOCAL BUS CONTROLLER
- Multiplexed or non-multiplexed address and data buses
- Connecting 8- and 16-bit devices
- Burst support
- GPCM, UPMs states machines
- NAND flash controller
INTEGRATED DMA CONTROLLERS
- Priority between the 4 channels
- Scatter / gathering
- Selectable hardware enforced coherency
- Ability to start DMA from external 3-pin interface
PCI EXPRESS INTERFACE
- Acting as a bridge when Root Complex
- Transaction ordering rules
- Programming inbound and outbound ATMUs
- Benefits of MSIs
- Low power management
- Configuration, initialization
- Enhanced error reporting
SERIAL RAPIDIO INTERFACE
- RapidIO port
- RapidIO doorbell and port-write unit
- Programming inbound and outbound ATMUs
SATA CONTROLLERS
- Support for SATA II extensions
- Bringing the SATA controller online/offline
- Native command queuing, command descriptor
- Interrupt coalescing
- Initialization steps
DATAPATH PROCESSING SUBSYSTEM
DPAA OVERVIEW
- Data formats
- Frame formats
- Packet walk through
- DPAA Configuration and initialization
QUEUE MANAGER
- Objectives if this accelerator
- Structure of frame queues
- Active and suspended frame queues
- Frame queue descriptor, frame queue descriptor cache
- Frame queue state machine
- Work queues and channels
- Enqueue and dequeue portals
- Utilization of rings
- Dequeue dispatcher operation
- Message ring
- Congestion avoidance, Weighted Random Early Discard
- Order definition point implementation
BUFFER MANAGER
- Objectives if this accelerator
- Central resource pool management function
- Per-pool stockpile
- CoreNET software portals
- Direct connect portals
- Buffer Pool State Change Notifications
FRAME MANAGER
- Objectives if this accelerator
- FMAN submodules
- Rx BMI features
- Tx BMI features
- Offline parsing, host command features
- Frame processing manager
- FMan controller
- Parser
- Key generator
- Policer
DATA PATH THREE-SPEED ETHERNET CONTROLLERS
- Frame format with and without VLAN option
- Connection to packet FIFO interface
- Physical interfaces
- 256-entry hash table for unicast and multicast
- Accessing PHY registers
- RMON statistic counters, carry registers
- Client IEEE1588 timers
10-GIGABIT MAC
- XAUI interface to PHY
- Multicast address filtering
- Dynamic inter packet gap (IPG) calculation
- MAC address insertion
- Support for VLAN
- IEEE 1588 timestamping
RAPIDIO MESSAGE MANAGER
- 2 inbox/outbox mailboxes (queues) for data and one doorbell message structure
- Multicasting
- Outbound segmentation units
SECURITY ENGINE
- Introduction to DES, 3DES and AES algorithms
- Job management using QMan interface
- Input / output rings
- Cryptographic operations
- Data movement, FIFOs
- Scatter / gather DMA
- Selecting the authentication / cryptographic algorithm
- Run Time Integrity Checking
- Example, implementing IPSec
PATTERN MATCHER
- Objective of this unit, identifying signatures in incoming gigabit streams
- Connection to QMan and BMan
- Ability to track stateful relationships between patterns found in the data it scans
- Updating the pattern database
- Definition of a regular expression
- Comparing the string under inspection with the programmed patterns
- Processing pipeline, work units
- Pattern Matcher Frame Agent
- Pattern description block caching
- Key Element Scanner
- Data Examination Engine
- Stateful Rule Engine
GLOBAL FUNCTIONS, DEVELOPMENT AND DEBUG
PERFORMANCE MONITOR AND DEBUG FEATURES
- Introduction to NEXUS specification
- NEXUS Aurora link
- Event processing unit
- Watchpoint facility
- Trace buffer
- Event Combining for the Creation of Advanced Triggers
- Cross-Functional Debug Components
- DDR SDRAM interface debug, measuring per-master bandwidth
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