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FCQ7 T4240 QorIQ implementation

This course covers NXP QorIQs T4240 & T4160

Objectives
  • This course has 6 main objectives:
    • Describing the hardware implementation, particularly the boot sequence and the DDR3 controller
    • Understanding the features of the internal interconnect and related units and mechanisms such as PAMU, CPC and stashing
    • Explaining the standard bus interface controllers, PCIe, SRIO, USB, SATA and MMC-SD
    • Describing the units which are interconnected to other modules, such as clocking, interrupt controller and DMA controller, because the boot program generally has to modify the setting of these units
    • Clarifying the operation of the Datapath Acceleration Architecture that assists the processor core in taking in charge buffer allocation, queue management, frame management and particularly incoming frame classification, pattern searching, and encryption
    • Describing the various debug units and their utilization to fix errors in a multicore / multimaster SoC.

  • Products and services offered by AC6:
    • AC6 is able to assist the customer by providing consultancies
    • Typical expertises are done during board bringup, hardware schematics review, software debugging, performance tuning.
    • Note that AC6 has delivered several consultancies on NXP Netcomm SoCs to companies developing avionic equipments.
A more detailed course description is available on request at training@ac6-training.com
This document is necessary to tailor the course to specific customer needs and to define the exact schedule.
  • Experience of a 32-bit processor or DSP is mandatory.
  • Note that the e6500 Power core is covered in a separate course reference FCC4 - e6500 implementation course.
  • Theoretical course
    • PDF course material (in English) supplemented by a printed version for face-to-face courses.
    • Online courses are dispensed using the Teams video-conferencing system.
    • The trainer answers trainees' questions during the training and provide technical and pedagogical assistance.
  • At the start of each session the trainer will interact with the trainees to ensure the course fits their expectations and correct if needed
  • Any embedded systems engineer or technician with the above prerequisites.
  • The prerequisites indicated above are assessed before the training by the technical supervision of the traineein his company, or by the trainee himself in the exceptional case of an individual trainee.
  • Trainee progress is assessed by quizzes offered at the end of various sections to verify that the trainees have assimilated the points presented
  • At the end of the training, each trainee receives a certificate attesting that they have successfully completed the course.
    • In the event of a problem, discovered during the course, due to a lack of prerequisites by the trainee a different or additional training is offered to them, generally to reinforce their prerequisites,in agreement with their company manager if applicable.

Course Outline

  • Internal architecture
  • Coherency subdomains
  • Memory map, local access windows
  • Highlighting data paths inside the T4240
  • e6500 core integration
  • DC and AC electrical characteristics
  • Reset causes
  • Reset configuration words source
  • Pre-boot loader
  • PCIe , SRIO Host / Agent configuration
  • Clocking, system clock domains
  • SerDes high speed lanes configuration
  • Objectives of trust architecture
  • Internal boot ROM, secure boot sequence
  • Code signing
  • External tamper detection
  • Run time integrity checker
  • Secure debug controller
  • Cache operation, write-through or write-back operation
  • Entry locking
  • Operation as memory-mapped SRAM
  • Partitioning between coherency domains
  • Stashing, address-based or CoreNet signalled
  • Controlling master access permissions through Logical I/O Device Number
  • Address translation
  • Operation mode translation
  • Steps in processing of DSA operations by PAMU
  • PAMU gate closed state
  • Interrupt nesting
  • Description of the 4 timers / counters
  • Message interrupts
  • e6500-to-e6500 interrupt capability
  • Interrupt assignment
  • Description of the NS16450/16550 compliant Uarts
  • I2C controller
  • eSPI controller
  • Interface to SD and MMC cards
  • Transfer protocol, single block, multiple block read and write
  • Internal and external DMA capabilities
  • Host or device support
  • High-speed operation
  • EHCI support, scheduling the various transactions into frames
  • Integrated PHY
  • Jedec specification basics
  • DDR3 fly-by architecture, write leveling
  • Reset sequence, dynamic ODT, ZQ calibration
  • Bank activation, read, write and precharge timing diagrams, page mode
  • Initial configuration following Power-on-Reset
  • Timing parameters programming
  • Initialization routine
  • Tuning the performance of the DDR3 controller
  • Testing the memory using patterns
  • Functional muxing of pins between NAND, NOR, and GPCM
  • Data Buffer Control
  • Normal GPCM FSM
  • NOR flash FSM
  • NAND flash FSM
  • Boot from NAND
  • Priority between the 4 channels
  • Support for cascading descriptor chains
  • Scatter / gathering
  • Acting as a bridge when Root Complex
  • Transaction ordering rules
  • Programming inbound and outbound ATMUs
  • Benefits of MSIs
  • Configuration, initialization
  • SR-IOV implementation, Alternative Routing ID
  • RapidIO port
  • Accept-all mode of operation
  • RapidIO doorbell and port-write unit
  • Accessing configuration registers via RapidIO packets
  • Programming inbound and outbound ATMUs
  • Chip-to-chip connection to FPGA, ASIC or TCAM
  • 64B/67B data encoding and scrambling
  • Using software portals to interact between software and hardware
  • Guaranting lane alignment, synchronizing of the scrambler, clock compensation through metaframes
  • Built in statistics counters and error counters
  • SATA basics
  • Support for SATA II extensions
  • Electrical specification
  • Bringing the SATA controller online/offline
  • Native command queuing, command descriptor
  • Definitions: buffer, buffer pool, frame, frame queue, work queue, channel
  • Frame formats
  • DPAA Configuration and Initialization
  • Objectives if this accelerator
  • Frame description
  • Frame queue descriptor, frame queue descriptor cache
  • Frame queue state machine
  • Work queues and channels
  • Enqueue and dequeue portals
  • Sequences to understand how frames a enqueued / dequeued
  • Class and intra-class scheduling rules
  • Stash transaction flow control and scheduling
  • Congestion avoidance
  • Order definition point implementation
  • Traffic shaping through CEETM
  • Objectives if this accelerator
  • Central resource pool management function
  • External linked list LIFO
  • Direct connect portals
  • Buffer Pool State Change Notifications
  • Objectives if this accelerator, parsing, classifying and distributing in-line/off-line packet
  • Rx BMI features
  • Tx BMI features
  • Offline parsing, host command features
  • Frame processing manager
  • FMan controller
  • Host commands
  • Parser
  • Key generator
  • Policer
  • New features:
    • IP fragmentation / re-assembly
    • Header manipulation
    • Autonomous 802.1qaz
    • Data center bridging
    • Ingress multicast
  • Physical interfaces
  • MAC address recognition
  • Accessing PHY registers, clause 45
  • Priority Flow Control
  • RMON statistic counters, carry registers
  • 2 inbox/outbox mailboxes (queues) for data and one doorbell message structure
  • Multicasting
  • Outbound segmentation units
  • Introduction to DES, 3DES and AES algorithms
  • Job management using QMan interface
  • Job descriptor parsing
  • Sharing descriptors
  • Selecting the authentication / cryptographic algorithm
  • Run Time Integrity Checking
  • Public Key Hardware Accelerator (PKHA)
  • SNOW 3G Accelerator
  • Data Encryption Standard Accelerator (DES)
  • Cyclic Redundancy Check Accelerator (CRCA)
  • Message Digest Hardware Accelerator (MDHA)
  • Elliptic Curve Cryptographic Functions
  • Objective of this unit, identifying signatures in incoming gigabit streams
  • Connection to QMan and BMan
  • Support for wildcarding with no pattern explosion
  • Updating the pattern database
  • Definition of a regular expression
  • Pattern Matcher Frame Agent
  • Pattern description block caching
  • Key Element Scanner, trigger stage, confidence stage
  • Data Examination Engine
  • Stateful Rule Engine, Stateful Rule Physical Structure, SRE instruction set
  • NEXUS Aurora link
  • Event processing unit
  • Chaining, triggering
  • Watchpoint facility
  • Trace buffer
  • Cross-Functional Debug Components
  • CoreNet debug
  • OCeaN debug
Duration
6 days
Cost
3250 € HT
Calendar
Session calendar
Inquire

To book a training session or for more information, please contact us on info@ac6-training.com.

Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.

You can also fill and send us the registration form

This course can be provided either remotely, in our Paris training center or, worldwide, on your premises.

Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 2 working days before the course start (1 week for face-to-face courses).

Last update of course schedule: 15 November 2021

Booking one of our trainings is subject to our General Terms of Sales