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Objectives
- This course has the following objectives:
- Describing the hardware implementation, particularly the boot sequence and the DDR3 controller
- Understanding the features of the internal interconnect and related units and mechanisms such as PAMU, CPC and stashing
- Explaining the standard bus interface controllers, PCIe, USB, SATA and MMC-SD
- Describing the units which are interconnected to other modules, such as clocking, interrupt controller and DMA controller, because the boot program generally has to modify the setting of these units
- Clarifying the operation of the Datapath Acceleration Architecture that assists the processor core in taking in charge buffer allocation, queue management, frame management and particularly incoming frame classification, pattern searching, and encryption
- Describing the various debug units and their utilization to fix errors in a multicore / multimaster SoC.
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A more detailed course description is available on request at training@ac6-training.com |
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This document is necessary to tailor the course to specific customer needs and to define the exact schedule. |
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