Training MPC8308 implementation: This course covers the PowerQUICC II Pro MPC8308

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FPQ4MPC8308 implementation
This course covers the PowerQUICC II Pro MPC8308
Objectives
  • The course explain the architecture of the MPC8308, particularly the operation of the coherency module that interconnects the e300 to memory and high-speed interfaces.
  • Cache coherency protocol is introduced in increasing depth.
  • The e300 core is viewed in detail, especially the MMU .
  • The boot sequence and the clocking are explained.
  • The course focuses on the hardware implementation of the MPC8308.
  • A long introduction to DDR SDRAM operation is done before studying the DDR1/2 SDRAM controller.
  • The course describes the sophisticated QoS mechanisms supported by the eTSEC Ethernet Controllers.
  • Implementation of Precise Time Protocol is also explained.
  • Generation of a Linux image and Root File System by using LTIB can also be included into the training.

  • Products and services offered by ACSYS:
    • ACSYS is able to assist the customer by providing consultancies
    • Typical expertises are done during board bringup, hardware schematics review, software debugging, performance tuning.
    • Note that ACSYS has delivered several consultancies on NXP Netcomm SoCs to companies developing avionic equipments.
A more detailed course description is available on request at training@ac6-training.com

A lot of programming examples have been developed by ACSYS to explain the boot sequence and the operation of complex peripherals, such as USB and Ethernet.
•  They have been developed with Diab Data compiler and are executed using Lauterbach debugger.
  • Theoretical course
    • PDF course material (in English) supplemented by a printed version for face-to-face courses.
    • Online courses are dispensed using the Teams video-conferencing system.
    • The trainer answers trainees' questions during the training and provide technical and pedagogical assistance.
  • At the start of each session the trainer will interact with the trainees to ensure the course fits their expectations and correct if needed
  • Any embedded systems engineer or technician with the above prerequisites.
  • The prerequisites indicated above are assessed before the training by the technical supervision of the traineein his company, or by the trainee himself in the exceptional case of an individual trainee.
  • Trainee progress is assessed by quizzes offered at the end of various sections to verify that the trainees have assimilated the points presented
  • At the end of the training, each trainee receives a certificate attesting that they have successfully completed the course.
    • In the event of a problem, discovered during the course, due to a lack of prerequisites by the trainee a different or additional training is offered to them, generally to reinforce their prerequisites,in agreement with their company manager if applicable.

Course Outline

  • Internal architecture
  • Highlighting data paths inside the MPC8308
  • Software migration from MPC8XX/MPC82XX/MPC85XX families
  • Application examples
  • Superscalar operation, out-of-order execution, register renaming, serializations, isync instruction
  • Branch processing unit: static prediction vs dynamic prediction
  • Load / store buffers
  • Sync and eieio instructions, determining where eieio is really required
  • Store gathering mechanism
  • Cache basics
  • L1 caches
  • Cache coherency mechanism, snooping, related signals
  • The MEI state machine
  • Management of cache enabled pages shared with DMAs
  • Software enforced cache coherency
  • Cache flush routine
  • PowerPC architecture specification, the 3 books UISA, VEA and OEA
  • Addressing modes, load / store instructions
  • Floating point arithmetical instructions
  • The PowerPC EABI
  • Linking an application with Diab Data
  • Introduction to real, block and segmentation / pagination translations
  • Memory attributes and access rights definition
  • TLBs organization
  • Segment-translation
  • Page-translation
  • MMU implementation in real-time sensitive applications
  • Critical interrupt, automatic nesting
  • Exception management mechanism
  • Requirements to allow exception nesting
  • JTAG emulation, restrictions
  • Hardware breakpoints
  • Power management control
  • Configuration signals sampled at reset
  • Utilization of the I2C boot sequencer
  • Clocking
  • Address translation and mapping
  • Arbiter and bus monitor
  • Timers, software watchdog timer, Real time clock module, Periodic Interval Timer, General Purpose Timers
  • Definition of interrupt priorities
  • System critical interrupt
  • Interrupt management, vector register
  • Requirements to support nesting
  • DDR-SDRAM operation
  • Jedec specification basics
  • Command truth table
  • Bank activation, read, write and precharge timing diagrams, page mode
  • Initial configuration following Power-on-Reset
  • Address decode
  • Timing parameters programming
  • Multiplexed or non-multiplexed address and data buses
  • Dynamic bus sizing
  • GPCM, UPMs states machines
  • Nand Flash Controller
  • Booting from NAND flash
  • Multi-block transfers
  • Moving data by using the dedicated DMA controller
  • Dividing large data transfers
  • Card insertion and removal detection
  • Implementation of a unique VC
  • Selectable operation as agent or root complex
  • Address translation
  • Transfer control descriptor format
  • Channel service request
  • Channel-to-channel linking mechanism
  • Scatter/gather DMA processing
  • Dual-role (DR) operation
  • EHCI implementation
  • ULPI interfaces to the transceiver
  • Endpoints configuration
  • Frame format with and without VLAN option
  • MAC address recognition
  • Interface with the PHY
  • Buffer descriptors management
  • TCP/IP Offload Engine
  • Quality of service support
  • IEEE1588 frame timestamping
  • UART
  • I2C
  • SPI controller
  • Introducing the tools required to generate the kernel image
  • What is required on the host before installing LTIB
  • Common package selection screen
  • Common target system configuration screen
  • Building a complete BSP with the default configurations
  • Creating a Root Filesystems image
  • e-configuring the kernel under LTIB
  • Selecting user-space packages
  • Setup the bootloader arguments to use the exported RFS
  • Debugging Uboot and the kernel by using Trace32
  • Command line options
  • Adding a new package
  • Other deployment methods
  • Creating a new package and integrating it into LTIB
    • A lot of labs have been created to explain the usage of LTIB
Duration
5 days
Inquiry

This course can be scheduled upon request. Click the 'Inquire' button to contact us.

More

To book a training session or for more information, please contact us on info@ac6-training.com.

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This course can be provided either remotely, in our Paris training center or worldwide on your premises.

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