RT5	Zephyr Real Time Programming

Real-time programming applied to the Zephyr operating system

Objectives Overview of the Cortex-M (ARM v7/v8-M Architecture) Discover the concepts of real time multitasking Understand Real Time constraints Determinism Preemption Interrupts Understand the Zephyr kernel Services Learn how to develop and debug Zephyr applications

Course environment Convenient course material ST STM32L562E-DK Discovery Example code, labs and solutions are provided to the attendees Prerequisites Good C programming skills (see our course L2 - C language for Embedded MCUs course) You may be interested (see our course AAM - ARM Cortex-M Architecture course)

Duration Total: 4 days From 40% to 50% of training time is devoted to practical activities Some Labs may be completed between sessions and are checked by the trainer on the next session

First Day Cortex-M Overview Introduction to ARM v7/v8-M Architecture ARM Cortex-M core Exceptions Interrupts Security Extension Memory Protection Unit Synchronization and Semaphores Introduction to Real Time Base real time concepts The Real Time constraints Multi-task and real time Getting Started with Zephyr Overview Source Tree Structure Creating an application Application Configuration Building an application Run an application Custom Board, Devicetree and SoC definition Debug Second Day Scheduling Concepts Scheduling Algorithm Cooperative Time Slicing Preemptive Time Slicing Scheduler Locking Thread Sleeping Busy Waiting Threads Lifecycle Thread States Thread Stack objects Thread Priorities Thread Options Thread Custom Data Implementation Runtime statistics Configuration options Thread safe data structures Need for specific data structures Thread safe data structures Linked lists Circular lists FIFOs Stacks Third Day

Memory Management Memory Heaps Synchronized Heap Allocator Low Level Heap Allocator Multi-Heap Wrapper Utility¶ System Heap Memory Slabs Concepts Defining a Memory Slab Allocating and Releasing a Memory Block Interrupts Concepts Multi-Level Interrupt handling Preventing Interruptions Offloading ISR Implementation Defining a regular ISR Defining a ‘direct’ ISR Implementation Details Data Structures Single-linked List Double-linked List Multi producer Consumer Packet Buffer Balanced Red/black Tree Ring Buffers Fourth Day Resource Management Concepts Atomic Services Semaphore Mutex Queues and Message Queues Mailboxes FIFOs and LIFOs Stacks Pipes Condition Variables Events Symmetric Multiprocessing Timing Kernel Timing Timers Defining a Timer Using a Timer Expiry Function Using a Timer Status Synchronization Trouble Shooting and Logging Checking for stack problems Common pitfalls Logging Usage Logging Panic Limitations and recommendations

 

Duration	Cost	Calendar
4 days	2500 € HT
Last update: 4 February 2022
This course, designed for face-to-face delivery, can be provided either in our Paris training center or, worldwide, on your premises. Scheduled classes are confirmed as soon as there is a confirmed booking.
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