PDF course material (in English) supplemented by a printed version.
The trainer answers trainees' questions during the training and provide technical and pedagogical assistance.
At the start of each session the trainer will interact with the trainees to ensure the course fits their expectations and correct if needed
Any embedded systems engineer or technician with the above prerequisites.
The prerequisites indicated above are assessed before the training by the technical supervision of the traineein his company, or by the trainee himself in the exceptional case of an individual trainee.
Trainee progress is assessed by quizzes offered at the end of various sections to verify that the trainees have assimilated the points presented
At the end of the training, each trainee receives a certificate attesting that they have successfully completed the course.
In the event of a problem, discovered during the course, due to a lack of prerequisites by the trainee a different or additional training is offered to them, generally to reinforce their prerequisites,in agreement with their company manager if applicable.
Objectives of MMC/eMMC specification, relationship with SD
High capacity devices
Speed class definition
Power Saving Sleep mode
Bus speed modes
Single ended signaling with 4 drive strengths
Signaling levels of 1.8V and 1.2V
Tuning concept for read operations
HS200 adjustable sampling host
Bidirectional strobe in HS400
Device reset to Pre-idle state
Boot area partitions
Device identification process
Power class selection
Power class selection
Accesses to the Replay Protected Memory Block
Command – Response – Data block structure tokens
Multiple-block read and write operations
Bus modes overview
• Secure mode, secure removal
Write protect management
Production state awareness
Replay Protected Memory Block, authenticated data transfers
Security protocol commands
Field firmware update
Device lock/unlock operation
eMMC FUNCTIONAL DESCRIPTION
High priority interrupt (HPI)
Real Time Clock
System data tagging
Dynamic device capacity
Optional volatile cache
Boot areas that will automatically stream data when using defined boot modes
Context writing interruption
HOST CONTROLLER INTERFACE
Example of NXP uSDHC
Relying on DMA to transfer data blocks
1400 € HT
This course, designed for face-to-face delivery, can be provided either in our Paris training center or, worldwide, on your premises.
Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 1 week before the course start.