ORIGINS OF THE SATA INTERFACE
- Parallel ATA limitations
- Faster HDD access and logical block addressing (LBA)
- ATAPI for support of other peripheral devices
- Programmed Input / output, direct memory access (UDMA)
- Revisions of the SATA specification
- Compatibility with SAS
SATA ARCHITECTURE
- Architectural layering
- Hot plugging
- Port multiplier
- Usage model description
PHYSICAL LAYER
- Cable and connectors
- Analog front end
- Electrical signalling
- Separate point-to-point AC-coupled LVDS links
- Spread Spectrum Clocking
- Elastic buffer
- Loopback mode
- Test pattern requirements
- Testing Gen3
- Jitter considerations
- Explaining the various tests used to qualify transmitter and receiver
OUT-OF BAND AND PHY POWER STATES
- COMRESET sequence
- COMINIT sequence
- COMWAKE sequence
LINK LAYER
- 8b/10b coding
- Scrambling
- Primitives description and utilization
- Arbitration sequence
- FIS flow control
- Transitions to low power modes
ATA REGISTERS
- PATA emulation
- Interrupt virtualization
TRANSPORT LAYER
- Introduction to FIS transfer
- Interaction with Command layer
- Retry protocol
PHY INTERFACE FOR SATA 3 (PIPE)
- Possible PIPE clocks and data bus widths
- Reset sequence
- Power management
- Changing signalling rate
- Error detection
- Loopback
ADVANCED HOST CONTROLLER INTERFACE (AHCI 1.3)
- System memory structures
- Native Command Queuing
- FIS-based switching
- Command completion coalescing
- Power management
- Interrupt management
- Data transfer operation
- Error reporting
COMMANDS
- ATA-8 command set
- Reset protocol, diagnostic protocol, PIO protocol, DMA protocol, PACKET protocol
- First party DMA
- Boot sequence capture and analyzis
registration form
