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Related Courses
eMMC 5.0
Serial ATA III
Universal Flash Storage (UFS 2.0)
SD UHS II (Ultra High Speed II)
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SD UHS II (Ultra High Speed II)
IS5
SD UHS II (Ultra High Speed II)
This course covers UHS-II which is the enhanced version of SD
Objectives
This course explains how legacy SD commands are transported over UHS II.
The hardware layer is detailed, including the analog part.
The link layer operation is explained through sequences clarifying flow control and acknowledgement mechanisms.
The course describes the low power modes.
The enumeration and configuration for a point-to-point or ring topology is studied.
Data protection system is also covered.
This training has been delivered several times to companies developing SoCs for wireless / consumer market.
A more detailed course description is available on request at
training@ac6-training.com
Prerequisites
Experience of mass-storage interface, such as SD/MMC or USB mass storage class is recommended.
OVERVIEW
Description of a NAND flash
Connection topologies
Interface speed
Protocol layers
Transactions
PHYSICAL LAYER
Range definition for data rates
Impedance and termination scheme
Line states
8b10b coding scheme
Control symbols
Test modes, loopback
LINK LAYER
Packet framing
Message packets
Physical Lane State Machine
Data Link State Machine
Power management
Flow control
Data integrity
Scrambling
Boot code loading
PHY-LINK INTERFACE
Interface signals
Clock generation
Timing diagrams
COMMON TRANSACTION LAYER
Packet formats
Transition to Dormant mode
Device initialization
Enumeration
Configuration
Registers mapping and description
Timing rules
SD TRANSACTION LAYER
Summary of legacy SD commands
Transaction Control and Management state machine
Basic transaction rules
Error handling
DATA PROTECTION SYSTEM
System and user password
Encryption key
DPS command set