ARM Cortex-A and R Architecture (v7/v8) Training | Ac6 Training

ac6-training, un département d'Ac6 SAS
EN
✓EnglishFrench
 
go-up

ac6 › ac6-training › Processors › ARM Cores › ARM Cortex-A and R Architecture (v7/v8)
Inquire
AAAARM Cortex-A and R Architecture (v7/v8)
This course explains the ARM Cortex-A and R global architecture.
Objectives
  • Describing the ARM v7 and v8 architecture profiles A and R
  • Describing the various ARM Cortex-A and R processor architecture
  • Presenting the Hardware and Software implementation possibilities to learn how to create Cortex-A based applications
  • Detailing ARMv8 Security (TrustZone) and Virtualization (Hypervisor) features
  • This course provides all the prerequisites for the courses describing in details the various Cortex-A and Cortex-R cores and CPUs.
  • Convenient course material with space for taking notes
  • Demos targeting a Cortex-A9 based SoC
  • Familiarity with embedded C concepts and programming
  • Basic knowledge of embedded processors
  • Any embedded systems engineer or technician with the above prerequisites.
  • The prerequisites indicated above are assessed before the training by the technical supervision of the traineein his company, or by the trainee himself in the exceptional case of an individual trainee.
  • Trainee progress is assessed by quizzes offered at the end of various sections to verify that the trainees have assimilated the points presented
  • At the end of the training, each trainee receives a certificate attesting that they have successfully completed the course.
    • In the event of a problem, discovered during the course, due to a lack of prerequisites by the trainee a different or additional training is offered to them, generally to reinforce their prerequisites,in agreement with their company manager if applicable.

Course Outline

  • Introduction to ARM and the Architecture
  • The AArch32 Programmer’s Model
  • The AArch64 Programmer's Model
  • Exceptions
  • Memory Architecture
  • Caches
  • Versions and Implementations
  • ARMv4T
  • ARMv5TE
  • ARMv6
  • ARMv7
  • ARMv8
  • SecurCore
  • Architecture Extensions
  • Pipelines
  • Cycle Counting
  • Multi-processing
  • Cache maintenance
  • Cache coherency hardware
  • Interrupt distribution
  • Power saving modes
  • Memory system hierarchy
  • Software storage and upload
  • Four exception levels
  • Exception Link Registers
  • Register banking by exception level
  • Nesting on the same exception level
  • Exception type and exception origin
  • Syndrome registers used to provide status information to the exception handler
  • Exception return instruction
  • AArch64 Exception vector tables
  • Generic Interrupt Controller CPU Interface Registers
  • Interrupt Virtualization
  • Interrupt Handling to support Nesting
  • Single Processor / Multi-Task RTOS
  • Multi-CPU Exclusive Resource Management
  • Wait for Event / send Event
  • Wait for Interrupt
  • Multi-Processor / Multi-Task RTOS
  • Embedded Software Development
  • Libraries and Linkage
  • Target platforms
  • Memory ordering models
  • Barriers and synchronization
  • Cache policies
  • Operating system support
  • Booting
  • Introduction
  • Coding techniques
  • Profiling
  • Debug basics
  • Debug hardware
  • Invasive Debug
  • Non-invasive Debug
  • Standard Debug Techniques
  • Timing
  • Resources
  • Self-Hosted Debug
  • Debug State Instructions
  • Linked comparisons for Breakpoint/Watchpoint exception generation
  • Software Step exceptions
  • Routing debug exceptions
  • External debug, cross-triggering
  • Embedded Trace Macrocell architecture
  • ARMv7 MMU and LPAE compatibility
  • LPAE enhancements to adapt to AArch64
  • Supporting up to 48 bits of VA per TTBR
  • Access permission checking
  • Supporting up to 48 bits of IPA and PA spaces
  • VMSAv8-64 address translation system
  • Memory translation granule size
  • Descriptor page table organization, descriptor format
  • Hierarchical control of Secure or Non-secure memory accesses
  • Compatibility with ARMv7
  • Security model when EL3 is using AArch64
  • Trapping to EL3 using AArch64
  • Re-entrant mode
  • Secure exception management, trapping
  • Asynchronous exception routing and control
  • New hypervisor privilege level on non-secure side
  • Re-entrant mode
  • Virtualization Extension Effect on MMU
    • Second stage MMU
    • I/O MMU
    • Managing external masters programmed by the guest OS without an I/O MMU
  • Emulation support
  • Hypervisor exception management, trapping
  • Asynchronous exception routing and control
  • Resource management
  • Virtualization modes
    • Para virtualization versus full virtualization
    • Separation kernels
    • Partitioning kernels
    • Operating-system virtualization (containers)
    • Existing hypervisors (Xen, KVM, ...)
Duration
4 days
Inquiry

This course can be scheduled upon request. Click the 'Inquire' button to contact us.

More

To book a training session or for more information, please contact us on info@ac6-training.com.

Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.

You can also fill and send us the registration form

This course can be provided either remotely, in our Paris training center or worldwide on your premises.

Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 1 week before the course start.

Last update of course schedule: 23 February 2026

Booking one of our trainings is subject to our General Terms of Sales

Related Courses