Programming

What are Safety & Security in Embedded Systems?

Cybersecurity and functional safety work together for connected products and industrial IoT. Anchored in the EU Cyber Resilience Act (CRA) and standards like IEC 62443, IEC 61508, and ISO 26262 (plus ETSI EN 303 645 and NIS2), the goal is to prevent hazards, withstand attacks, and keep devices dependable throughout their lifetime—from concept and development to updates in the field.

Modern platforms provide strong building blocks out of the box: secure boot chains (TF-A/U-Boot, HAB/AHAB, SBSFU/TF-M), isolation with TrustZone-M and OP-TEE, and Linux hardening features (SELinux/AppArmor, dm-verity/IMA, namespaces, seccomp). On the safety side, practices like MISRA/CERT coding, static analysis, FMEA/FTA, watchdogs, and CRC/ECC reduce faults without slowing development.

Our ac6 training courses help you master this ecosystem—covering risk and threat analysis, SBOM/VEX and vulnerability handling, key management and secure update/rollback, Linux/MCU hardening and TrustZone partitioning, and the safety lifecycle with evidence (plans, traceability, safety case). The outcome: products that are both secure and safe, ready for real-world assessments.

ac6-formation provides trainings on the various languages used in embedded systems. We propose courses on C, C++, Java and Python. Our coursse are tailored to the use of these languages in the embedded world context, with exercises targeting these environments.

The complexity of computer systems led more and more to the use of standard tools to support their specification, design and development. These tools are based, where possible, on standard methods and languages​​.

Ac6-training offers training on the most common modeling language UML (Unified Modeling Language); these courses are tailored to the industrial and embedded systems environment and the specific needs of real-time applications.

We also offer training on management tools for the software development process, as Eclipse.

Creating systems that work in real-time is a specific challenge. That's why ac6-training provides a range of courses to explain you all the specific techniques and tools to use in this context.

A microcontroller executes instructions one after another. An FPGA does not: it becomes the circuit you describe to it. A thousand operations can proceed at once, because they occupy a thousand distinct areas of silicon.

That is where the whole difficulty of learning lies. You are not writing a program, you are describing hardware. VHDL and SystemVerilog look like programming languages and are not: a loop is not a repetition in time but a replication in space, and a signal is not a variable. Beginners who approach VHDL as if it were C produce circuits that simulate correctly and fail to meet timing.

When an FPGA is the right answer

Three cases keep coming back: genuine parallelism, when dozens of channels must be handled simultaneously; deterministic latency, when a response is due within tens of nanoseconds, which no software interrupt can guarantee; and interfaces nobody sells, a proprietary protocol or a sensor with an unusual format.

Outside those cases a microcontroller stays simpler, cheaper and quicker to bring up. An FPGA is paid for in design time and in power consumption.

Describe, verify, integrate

Design is done in VHDL or SystemVerilog. SystemC comes in higher up, to explore an architecture before freezing the RTL.

Verification often weighs more than design itself. UVM is the industry standard methodology for building reusable testbenches: an unverified circuit is not a finished circuit.

Finally, most current FPGAs carry a processor, either hardened into the silicon like the Cortex-A9 in Zynq and Cyclone V devices, or synthesised into the fabric like MicroBlaze, Nios, Mico32 or a RISC-V core. Designing for these parts means splitting a function between software and hardware, and making the two talk to each other.

Our courses

VHDL Language Basics (V1) and Advanced VHDL for FPGA (V2) form the main path, from syntax to design methodology. SystemVerilog (U1) and UVM (U2) cover the verification side, Design with SystemC (V3) high-level modelling, and FPGA Optimization (V4) the work on performance and area. Programmable components fundamentals (V0) is the entry point for those starting from nothing.

On the device side, the courses follow the main vendors: AMD Zynq (HX5) and MicroBlaze (HX4), Cyclone V Cortex-A9 (ALT1) and Nios (ALT2), Lattice Mico32 (H1) and Diamond (H2), Microchip SmartFusion2 (MSP). RISC-V Architecture (RV1) covers the instruction set that has become hard to avoid for synthesised cores.

Hands-on work runs on real boards on site, and remotely on remotely accessible hardware or on the simulation tools we develop. A timing problem is only understood by watching it happen.