Programming

What are safety and security in embedded systems?

Cybersecurity and functional safety work together in connected products and industrial IoT. The EU Cyber Resilience Act (CRA) and standards such as IEC 62443, IEC 61508 and ISO 26262, alongside ETSI EN 303 645 and NIS2, set a common goal: prevent hazards, withstand attacks and keep devices dependable for their whole lifetime, from concept and development through to updates in the field.

Which building blocks do modern platforms provide?

Silicon vendors and open-source projects ship most of the foundations: secure boot chains (TF-A/U-Boot, HAB/AHAB, SBSFU/TF-M), isolation through TrustZone-M and OP-TEE, and Linux hardening features such as SELinux/AppArmor, dm-verity/IMA, namespaces and seccomp. On the safety side, MISRA/CERT coding rules, static analysis, FMEA/FTA, watchdogs and CRC/ECC catch faults early, without slowing development down.

What do our training courses cover?

Our Ac6 courses walk through the whole ecosystem: risk and threat analysis, SBOM/VEX and vulnerability handling, key management, secure update and rollback, Linux and MCU hardening, TrustZone partitioning, and the safety lifecycle with the evidence an assessor expects, including plans, traceability and the safety case. You leave able to build products that are both secure and safe, and ready for a real assessment.

The language you write embedded code in shapes what the compiler can check for you and what only shows up at run time. C still carries most firmware, C++ brings abstraction that costs nothing at run time when it is used correctly, and Python and Java have their place in tooling and in application layers.

Our courses cover C for microcontrollers, classic and modern C++ up to C++20, OpenCL for parallel computing, Python, and Java for industrial and Android development. Each one is built around the constraints of embedded targets: limited memory, no dynamic allocation, and code that has to be reviewable.

The details are what the courses spend time on: undefined behavior and what the optimizer is allowed to do with it, alignment and aliasing rules, move semantics and RAII without dynamic allocation, template cost at compile time versus run time, and the MISRA rules that exist because these traps are real.

Past a certain size, an embedded system fails less from bad code than from decisions taken without a way to check them. Modeling and safety analysis exist to make those decisions reviewable before the hardware is built.

UML gives a shared notation for architecture and real-time behavior. Safety work adds the methods that certification expects: hazard analysis, FMEA and fault trees, traceability from requirement to test, and the evidence an assessor asks for. Neither replaces engineering judgment, both make it inspectable.

Our courses cover software architecture with UML, real-time modeling, and the safety lifecycle for critical systems, including the standards that govern it and the documents a project has to produce.

Real time is not about speed. It is about proving that a response happens within a bounded delay, every time. That constraint changes how you design tasks, share data between them and handle interrupts, and it has to be settled before the architecture is fixed.

Our courses cover the kernels used in the field, FreeRTOS, Zephyr, Eclipse ThreadX and RT-Thread, along with multicore programming, AUTOSAR and OSEK/VDX for automotive, and the vendor ecosystems from NXP and Nordic. Lab work runs on real boards or on simulated targets.

The failures are always the same ones: priority inversion where a low-priority task holds a mutex a high-priority one needs, stacks sized by guesswork until one overflows into a neighbor, critical sections long enough to miss a deadline, and ISRs doing work that belongs in a task. The courses treat these as the subject, not as footnotes.

An FPGA holds logic that you define yourself, reconfigured as the product evolves. It suits designs that need parallel processing, tight latency or interfaces no off-the-shelf processor provides. Modern devices combine that fabric with ARM cores on a single chip.

Our courses cover VHDL from the language basics through advanced design, the AMD Zynq and Altera Cyclone-V platforms, the Nios and Microblaze soft cores, and the Microchip SmartFusion2. Lab work runs on real boards, on the vendor toolchains you will use in production.

Below the language sits the part that decides whether a design meets timing: clock domain crossing and metastability, synthesis constraints, resource sharing between logic and DSP blocks, and reading a place-and-route report to find where the critical path actually is. The courses cover VHDL and SystemVerilog, UVM verification, and the vendor flows from Vivado and Quartus.