ARCHITECTURE OF KINETIS MCUs
- ARM core based architecture
- Description of K10, K20, K30, K40 and K60 SoC architecture
- Clarifying the internal data and instruction paths: AHB-lite interconnect, peripheral buses, AIPD bridges
- AMBA-to-IPS Re-use IP: ColdFire (AIPS) Controller
- Integrated memories
- SoC mapping
THE ARM CORTEX-M4 CORE
- V7-M core family
- Core architecture
- Freescale on-chip instruction and data cache
- Thumb-2 instruction set
- Exception behavior
- Basic interrupt operation, micro-coded interrupt mechanism
- Memory Protection Unit
V7-M DATA SIGNAL PROCESSING INSTRUCTIONS
- Multiply instructions
- Packing / unpacking instructions
- SIMD packed add/sub instructions
- SIMD combined add/sub instructions
- SIMD multiply and multiply accumulate instructions
- SIMD sum absolute difference instructions
- SIMD select instruction
- Saturation instructions
- Floating point unit
- Cortex Microcontroller Software Interface Standard (CMIS)
BECOMING FAMILIAR WITH THE IDE
- Acsys covers 3 iDEs: CodeWarrior, IAR and GCC / Lauterbach
- Thus the customer has just to indicate which one he has chosen
- Getting started with the IDE
- Parameterizing the compiler / linker
- Creating a project from scratch
- C start program
PROGRAMMING AND DEBUGGING
- Debug interface
- Programming
RESET, POWER AND CLOCKING
- Reset
- Clocking
- Operation modes
INTERNAL INTERCONNECT
- Crossbar switch
- Hardware Memory Protection Unit
- eDMA
HARDWARE IMPLEMENTATION
- Power pins
- Pinout
- GPIO module
INTEGRATED MEMORIES
- Flex memory, this module is not implemented in all Kinetis devices
- Internal SRAM
MEMORY INTERFACE
- Each Kinetis family supports either a subset or all the following controllers
- FlexBus
- eSDHC
- NAND flash controller
- DRAM controller
TIMERS
- Low Power Oscillator
- COP
- External Watchdog Monitor
- Periodic Interrupt Timer
- Low Power Timer
- Flex Timer
- Carrier Modulator Transmitter
ANALOG MODULES
- 16-bit Analog-to-Digital Converter and Programmable Gain Amplifier
- 12-bit Digital-to-Analog Converter
- Voltage Reference VREF
- High-Speed Comparator HSCMP
- Programmable Delay Block PDB
SECURITY AND INTEGRITY
- Hardware Cyclic Redundancy Check
- Memory-Mapped Cryptographic Acceleration Unit (MMCAU)
- Pseudo Random Number Generator
- Secure Real Time Clock
- DryIce and Tamper Detect
- Cryptographic Acceleration Unit
CONNECTIVITY AND COMMUNICATION
- DSPI
- UART
- I2C
- CAN modules
- USB
- Fast ethernet with IEEE1588
- ISO7816 smartcard interface
- I2S audio interface
USER INTERFACES
- Segment LCD controller
- Graphics LCD controller
- Capacitive touch sensing
registration form
