STR5STM32 F1-Series implementation
This course covers STM32F100XX, STM32F101XX, STM32F103XX, STM32F105XX and STM32F107XX ARM-based MCU family
Objectives
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- This course provides an overview of the ARM Cortex-M3 core. Our course reference RM2 - Cortex-M3 implementation course details the operation of this core.
- The following courses could be of interest:
- USB Full Speed High Speed and USB On-The-Go, reference IP2 - USB 2.0 course
- Ethernet and switching, reference N1 - Ethernet and switching course
- IEEE1588, reference N2 - IEEE1588 - Precise Time Protocol course
- CAN bus, reference IA1 - CAN bus course
- SD / MMC, reference IS2 - eMMC 5.0 course
- Theoretical course
- PDF course material (in English) supplemented by a printed version for face-to-face courses.
- Online courses are dispensed using the Teams video-conferencing system.
- The trainer answers trainees' questions during the training and provide technical and pedagogical assistance.
- At the start of each session the trainer will interact with the trainees to ensure the course fits their expectations and correct if needed
- Any embedded systems engineer or technician with the above prerequisites.
- The prerequisites indicated above are assessed before the training by the technical supervision of the traineein his company, or by the trainee himself in the exceptional case of an individual trainee.
- Trainee progress is assessed by quizzes offered at the end of various sections to verify that the trainees have assimilated the points presented
- At the end of the training, each trainee receives a certificate attesting that they have successfully completed the course.
- In the event of a problem, discovered during the course, due to a lack of prerequisites by the trainee a different or additional training is offered to them, generally to reinforce their prerequisites,in agreement with their company manager if applicable.
Course Outline
- ARM core based architecture
- Description of STM32F10X SoC architecture
- Clarifying the internal data and instruction paths: AHB-lite interconnect, peripheral buses, AHB-to-APB bridges
- Integrated memories
- SoC mapping
- V7-M core family
- Core architecture
- Programming
- Exception behavior, exception return
- Basic interrupt operation, micro-coded interrupt mechanism
- Acsys covers 3 IDEs: Keil, IAR and GCC / Lauterbach
- Thus the customer has just to indicate which one he has chosen
- Getting started with the IDE
- Parameterizing the compiler / linker
- Creating a project from scratch
- C start program
- Debug interface
- Programming
- Power control
- Reset
- Clocking
- Low power modes
- Bus matrix
- DMA
- Power pins
- Pinout
- GPIO module
- External Interrupts
- Embedded flash memory
- Internal SRAM
- SDIO
- Flexible Static Memory Controller
- Advanced-control timers TIM1 and TIM8
- General-purpose timers (TIM2 to TIM5)
- General-purpose timers (TIM9 to TIM14)
- Basic timers (TIM6 and TIM7)
- Real Time Clock
- Independent Watchdog
- Window Watchdog
- 12-bit Analog-to-Digital Converter and Programmable Gain Amplifier
- 12-bit Digital-to-Analog Converter
- CRC calculation unit
- Device Electronic Signature
- SPI
- SPI in I2S mode
- UART
- I2C
- bxCAN modules
- USB FS
- Fast ethernet with IEEE1588
- ISO7816 smartcard interface
More
To book a training session or for more information, please contact us on info@ac6-training.com.
Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.
You can also fill and send us the registration form
This course can be provided either remotely, in our Paris training center or worldwide on your premises.
Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 1 week before the course start.
Last update of course schedule: 2 May 2016
Booking one of our trainings is subject to our General Terms of Sales