- This course has 5 main objectives:
- Describing the hardware implementation and highlighting the pitfalls
- Describing the ARM Cortex-M3 core architecture
- Becoming familiar with the IDE and low level programming
- Describing the units which are interconnected to other modules, such as clocking, interrupt controller and DMA controller, because the boot program generally has to modify the setting of these units
- Describing independent I/O modules and their drivers.
- Note that this course has been designed from the architecture of the most complex STM32 F1-Series device, the STM32F107.
- Consequently, a chapter has been designed by Acsys for each possible integrated IP.
- According to the actual reference chosen by the customer, some chapters may be removed.
- Products and services offered by ACSYS:
- ACSYS is able to assist the customer by providing consultancies. Typical expertises are done during board bringup, hardware schematics review, software debugging, performance tuning.
- ACSYS has also an expertise in FreeRTOS porting and uIP /LWIP stack or Interniche stack integration.
|A lot of programming examples are provided to help the attendee to become familiar with the topics taught in the course.
|Labs included in this course are conducted under the System Workbench for STM32 free IDE. For on-site courses, they can also be compiled and executed under two other IDEs: IAR and Keil
|A more detailed course description is available on request at email@example.com
|This document is necessary to tailor the course to specific customer needs and to define the exact schedule.