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ac6 >> ac6-training >> Processors >> ST processors >> STM32 F1-Series implementation Download as PDF Write us

STR5 STM32 F1-Series implementation

This course covers STM32F100XX, STM32F101XX, STM32F103XX, STM32F105XX and STM32F107XX ARM-based MCU family

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Objectives
  • This course has 5 main objectives:
    • Describing the hardware implementation and highlighting the pitfalls
    • Describing the ARM Cortex-M3 core architecture
    • Becoming familiar with the IDE and low level programming
    • Describing the units which are interconnected to other modules, such as clocking, interrupt controller and DMA controller, because the boot program generally has to modify the setting of these units
    • Describing independent I/O modules and their drivers.

  • Note that this course has been designed from the architecture of the most complex STM32 F1-Series device, the STM32F107.
  • Consequently, a chapter has been designed by Acsys for each possible integrated IP.
    • According to the actual reference chosen by the customer, some chapters may be removed.

  • Products and services offered by ACSYS:
    • ACSYS is able to assist the customer by providing consultancies. Typical expertises are done during board bringup, hardware schematics review, software debugging, performance tuning.
    • ACSYS has also an expertise in FreeRTOS porting and uIP /LWIP stack or Interniche stack integration.

A lot of programming examples are provided to help the attendee to become familiar with the topics taught in the course.
Labs included in this course are conducted under the System Workbench for STM32 free IDE. For on-site courses, they can also be compiled and executed under two other IDEs: IAR and Keil
A more detailed course description is available on request at training@ac6-training.com
This document is necessary to tailor the course to specific customer needs and to define the exact schedule.

  • Theoretical course
    • PDF course material (in English) supplemented by a printed version for face-to-face courses.
    • Online courses are dispensed using the Teams video-conferencing system.
    • The trainer answers trainees' questions during the training and provide technical and pedagogical assistance.
  • At the start of each session the trainer will interact with the trainees to ensure the course fits their expectations and correct if needed
  • Any embedded systems engineer or technician with the above prerequisites.
  • The prerequisites indicated above are assessed before the training by the technical supervision of the traineein his company, or by the trainee himself in the exceptional case of an individual trainee.
  • Trainee progress is assessed by quizzes offered at the end of various sections to verify that the trainees have assimilated the points presented
  • At the end of the training, each trainee receives a certificate attesting that they have successfully completed the course.
    • In the event of a problem, discovered during the course, due to a lack of prerequisites by the trainee a different or additional training is offered to them, generally to reinforce their prerequisites,in agreement with their company manager if applicable.

Course Outline

  • ARM core based architecture
  • Description of STM32F10X SoC architecture
  • Clarifying the internal data and instruction paths: AHB-lite interconnect, peripheral buses, AHB-to-APB bridges
  • Integrated memories
  • SoC mapping
  • V7-M core family
  • Core architecture
  • Programming
  • Exception behavior, exception return
  • Basic interrupt operation, micro-coded interrupt mechanism
  • Acsys covers 3 IDEs: Keil, IAR and GCC / Lauterbach
  • Thus the customer has just to indicate which one he has chosen
    • Getting started with the IDE
    • Parameterizing the compiler / linker
    • Creating a project from scratch
    • C start program
  • Debug interface
  • Programming
  • Power control
  • Reset
  • Clocking
  • Low power modes
  • Bus matrix
  • DMA
  • Power pins
  • Pinout
  • GPIO module
  • External Interrupts
  • Embedded flash memory
  • Internal SRAM
  • SDIO
  • Flexible Static Memory Controller
  • Advanced-control timers TIM1 and TIM8
  • General-purpose timers (TIM2 to TIM5)
  • General-purpose timers (TIM9 to TIM14)
  • Basic timers (TIM6 and TIM7)
  • Real Time Clock
  • Independent Watchdog
  • Window Watchdog
  • 12-bit Analog-to-Digital Converter and Programmable Gain Amplifier
  • 12-bit Digital-to-Analog Converter
  • CRC calculation unit
  • Device Electronic Signature
  • SPI
  • SPI in I2S mode
  • UART
  • I2C
  • bxCAN modules
  • USB FS
  • Fast ethernet with IEEE1588
  • ISO7816 smartcard interface